Devices including a p-i-n diode disposed adjacent a silicide in series with a dielectric material

A first memory level comprising:

• a plurality of first substantially parallel, substantially coplanar conductors formed above a substrate;
• a plurality of second substantially parallel, substantially coplanar conductors formed above the first conductors;
• a plurality of vertically oriented p-i-n diodes comprising semiconductor material;
• a silicide, silicide-germanide, or germanide layer disposed adjacent each of the vertically oriented p-i-n diodes;
• a plurality of dielectric material layers;
• and
• a plurality of memory cells, each memory cell comprising one of the vertically oriented p-i-n diodes and one of the dielectric material layers,
• wherein:
• each of the p-i-n diodes is disposed between one of the first conductors and one of the second conductors,
• each dielectric material layer is disposed between one of the first conductors and one of the p-i-n diodes or between one of the second conductors and one of the p-i-n diodes,
• each dielectric material layer is disposed between a first conductive layer and a second conductive layer, and
• the dielectric material layers are selected from the group consisting of HfO2, Al2O3, ZrO2, TiO2, La2O3, Ta2O5, RuO2, ZrSiOx, AlSiOx, HfSiOx, HfAlOx, HfSiON, ZrSiAlOx, HfSiAlOx, HfSiAlON, and ZrSiAlON.

A monolithic three dimensional memory array formed above a substrate, the array comprising:

• a) a first memory level monolithically formed above the substrate, the first memory level comprising:
• i) a plurality of first substantially parallel, substantially coplanar conductors extending in a first direction;
• ii) a plurality of second substantially parallel, substantially coplanar conductors extending in a second direction different from the first direction, the second conductors above the first conductors;
• iii) a plurality of vertically oriented p-i-n diodes formed of deposited semiconductor material, each vertically oriented diode disposed between one of the first conductors and one of the second conductors;
• iv) a plurality of silicide, silicide-germanide, or germanide layers disposed adjacent a corresponding one of the vertically oriented p-i-n diodes;
• v) a plurality of dielectric material layers, each disposed between a corresponding first conductive layer and a corresponding second conductive layer, wherein the dielectric material is selected from the group consisting of Hf02, Al2O3, ZrO2, TiO2, La2O3, Ta2O5, RuO2, ZrSiOx, AlSiOx, HfSiOx, HfAlOx, HfSiON, ZrSiAlOx, HfSiAlOx, HfSiAlON, and ZrSiAlON;
• and
• vi) a plurality of memory cells, each memory cell comprising one of the diodes and one of the dielectric material layers arranged in series;
• and
• b) a second memory level monolithically formed above the first memory level.