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US 2013/0104095 A1Published application
Integrated Circuit Routing with Compaction
AssigneePulsic Limited
InventorMark Waller
Life of this patent
Estimating the term…
Abstract
An iterative technique is used to automatically route nets and alter spacing of an integrated circuit design to achieve a fully routed and compact result. After identifying solid and hollow channels, the technique automatically places route paths to connect pins of cells in the solid channels, where route paths may be placed within the solid channels or hollow channels. The technique can reduce a width of at least one hollow channel when an entire space of the hollow channel is not occupied by a placed route path.
Claims1
An integrated circuit router system embodied using a nontransitory computer-readable medium comprising:
- a first code component to identify solid and hollow channels in a selected portion of an integrated circuit layout;
- and
- a second code component to automatically place route paths to connect pins of cells in the solid channels, where route paths may be placed within the solid channels or hollow channels.
Dependencies are inferred from the claim text.