Ramp signal generation circuit and ramp signal adjustment circuit

A ramp signal generation circuit, comprising:

• a first input terminal that receives a clock signal;
• a plurality of second input terminals that receive high-level or low-level signals, respectively, in accordance with a cycle of the clock signal;
• a capacitor;
• and
• a discharge and charge circuit that discharges and charges the capacitor and that outputs a ramp signal corresponding to a voltage generated by the capacitor, the discharge and charge circuit including:
• a discharge circuit that discharges the capacitor in synchronization with the clock signal;
• and
• a charge circuit that is configured with a plurality of paired resistors and switching elements connected between the capacitor and a power source voltage line, the charge circuit charging the capacitor through one of the resistors and one of the switching elements, wherein
• the discharge and charge circuit selects at least one of the plurality of second input terminals so as to change a value of a charge current for charging the capacitor through an ON and OFF operation of the switching elements by inputting the high-level signal to the selected one of the plurality of second input terminals.

A ramp signal adjustment circuit, comprising:

• a clock signal generation circuit that generates a clock signal by dividing a base clock signal;
• a signal output circuit that has a plurality of terminals and that outputs high-level or low-level signals from each of the plurality of terminals;
• a capacitor;
• and
• a discharge and charge circuit that discharges and charges the capacitor and that outputs a ramp signal corresponding to a voltage generated by the capacitor, the discharge and charge circuit including:
• a discharge circuit that discharges the capacitor in synchronization with the clock signal;
• and
• a charge circuit that is configured with a plurality of paired resistors and rectifying elements connected between the capacitor and the plurality of terminals, the charge circuit charging the capacitor through one of the resistors and one of the rectifying elements, wherein
• the discharge and charge circuit selects at least one of the plurality of terminals so as to change a value of a charge current for charging the capacitor by inputting the high-level signal to the selected one of the plurality of terminals.

A ramp signal adjustment circuit, comprising:

• a clock signal generation circuit that generates a clock signal by dividing a base clock signal;
• a signal output circuit that has a plurality of terminals and that outputs high-level or low-level signals from each of the plurality of terminals;
• a capacitor;
• and
• a discharge and charge circuit that discharges and charges the capacitor and that outputs a ramp signal corresponding to a voltage generated by the capacitor, the discharge and charge circuit including:
• a discharge circuit that discharges the capacitor in synchronization with the clock signal;
• and
• a charge circuit that is configured with a plurality of paired resistors and switching elements connected between the capacitor and a power source voltage line, the charge circuit charging the capacitor through one of the resistors and one of the switching elements, wherein
• the discharge and charge circuit selects at least one of the plurality of terminals so as to change a value of a charge current for charging the capacitor through an ON and OFF operation of the switching elements by inputting the high-level signal to the selected one of the plurality of terminals.