US 2013/0097575 A1 · Rescaling

Abstract

A novel method for designing an integrated circuit (“IC”) by rescaling an original set of circuits in a design of the IC is disclosed. The original set of circuits to be rescaled includes sequential nodes, combinational nodes, and interconnects. Each sequential node is associated with a phase of a clock. The method generates a rescaled set of circuits that includes multiple replica sets of the circuits. Each replica set of circuits includes sequential nodes, combinational nodes, and interconnects that are identical to nodes and interconnects in the original set of circuits. Each sequential node is associated with a phase of a clock that is at a fraction of the phase of its corresponding sequential element in the original set. The method connects nodes in each replica set of circuits to a logically equivalent node in another replica set. The method replaces the original set of circuits with the rescaled set of circuits.

Claims21

Dependent claims

1-30. (canceled)

Dependencies are inferred from the claim text.

Facts

Application

13/806,767Filed 6 Apr 2011

Priority

23 Jun 2010

Published

18 Apr 2013

Term ends

Not estimatedThe source records don’t support an estimate.

Classification6 codes

G06F 30/394
Circuit design at the physical level: routing
G06F 30/30
Computer-aided design [CAD]: circuit design
G06F 30/327
Circuit design at the digital level: logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
G06F 30/34
Circuit design: for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Rescaling

Life of this patent

Rescaling

Life of this patent

Abstract

Claims21