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AssigneeNational Taiwan University
InventorsValeriy Balabanov, Meng-Kai Hsu, Yao-Wen Chang
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A computer-implemented method to generate a placement for a plurality of instances for an integrated circuit (IC) by utilizing a novel weighted-average (WA) wirelength model, which outperforms a well-known log-sum-exp wirelength model, to approximate the total wirelength. The placement is determined by performing an optimization process on an objective function which includes a wirelength function approximated by the WA wirelength model. The method can be extended to generate a placement for a plurality of instances for a three-dimensional (3D) integrated circuit (IC) which considers the sizes of through-silicon vias (TSVs) and the physical positions for TSV insertion. With the physical positions of TSVs determined during placement, 3D routing can easily be accomplished with better routed wirelength, TSV counts, and total silicon area.
A computer-implemented method for generating a placement for a plurality of instances in an integrated circuit (IC), wherein positions of the plurality of instances are defined according to a set of coordinates, the method comprising using a computer to perform the steps of:
A non-transitory computer readable medium storing one or more programs for generating a placement for a plurality of instances in an integrated circuit (IC), wherein positions of the plurality of instances are defined according to a set of coordinates, said one or more programs comprising instructions, which when executed by a computer, cause the computer to:
Dependencies are inferred from the claim text.