Method for dummy metal and dummy via insertion
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHung-Yi LIU, Chung-Hisng WANG, Chih-Chieh CHEN, Jian-Yi LI
Life of this patent
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Abstract
A method of inserting dummy metal and dummy via in an integrated circuit design. The method includes inserting, by a computer, dummy metals using a place and route tool, wherein the place and route tool has timing-awareness to improve a timing performance of the integrated circuit design. The method further includes inserting, by the computer, dummy vias using a design-rule-checking utility separately from the inserting of the dummy metals, wherein at least one of the dummy vias has a different size than at least another of the dummy vias.
Claims20
A method of inserting dummy metal and dummy via in an integrated circuit design, comprising:
- inserting, by a computer, dummy metals using a place and route tool, wherein the place and route tool has timing-awareness to improve a timing performance of the integrated circuit design;
- and
- inserting, by the computer, dummy vias using a design-rule-checking utility separately from the inserting of the dummy metals, wherein at least one of the dummy vias has a different size than at least another of the dummy vias.
A method of inserting dummy metal and dummy via in an integrated circuit design, comprising:
- inserting, by a computer, dummy metals using a place and route tool, wherein the place and route tool has timing-awareness to improve a timing performance of the integrated circuit design, and the dummy metals have a length less than or equal to a predetermined maximum length;
- and
- inserting, by the computer, dummy vias using a design-rule-checking utility separately from the inserting of the dummy metals.
A method of inserting dummy metal and dummy via in an integrated circuit design, comprising:
- inserting, by a computer, dummy metals using a place and route tool, wherein the place and route tool has timing-awareness to improve a timing performance of the integrated circuit design;
- and
- inserting, by the computer, dummy vias using a design-rule-checking utility separately from the inserting of the dummy metals, wherein a space between adjacent dummy vias is from 0.07 microns (μm) and 0.09 μm.
Dependencies are inferred from the claim text.