Global clock handler object for hdl environment

A method comprising:

• simulating a design of an integrated circuit, wherein said simulating comprises executing, on a computer system, a first plurality of hardware design language (HDL) statements in a first module representative of a first functional block of the integrated circuit;
• executing a first clock statement, wherein the first clock statement is one of the first plurality of HDL statements;
• and
• a generating a simulation of a first clock signal responsive to execution of the first clock statement, wherein said generating is performed by a clock handler object executing on the computer system, wherein simulating the design of the integrated circuit includes simulating synchronizing operation of the first functional block to the first clock signal.

The method as recited in claim 16, further comprising:

• executing a second plurality of HDL statements in a second module representative of a second functional block of the integrated circuit;
• executing a second clock statement;
• and
• generating a simulation of a second clock signal responsive to execution of the second clock statement, wherein said generating is performed by the clock handler object executing on the computer system.

A method comprising:

• executing, on a computer system, a plurality of HDL statements of a testbench module, wherein executing the plurality of HDL statements includes:
• instantiating an HDL module corresponding to a device under test (DUT), wherein the DUT corresponds to a design of an integrated circuit described by the HDL module;
• executing a plurality of clock statements;
• generating a plurality of simulated clock signals responsive to executing the plurality of clock statements, wherein each of the plurality of simulated clock signals is instantiated responsive to execution of a corresponding one of the plurality of clock statements, and wherein said generating is performed by the clock handler object executing on the computer system;
• and
• simulating the plurality of simulated clock signals being provided to and synchronizing respective ones of a plurality of functional blocks of the DUT.