US 2013/0097567 A1 · CYCLE CUTTING WITH TIMING PATH ANALYSIS

Abstract

The timing cycles in a circuit design are identified and cut such that timing constraint paths in the circuit design are preserved. Timing cycles in the circuit design may be identified by traversing an adjacency list data structure, in which elements of the circuit design are represented as vertices interconnected by edges. Timing constraint paths may be distinguished from false timing paths using timing analysis, such as a greatest common path heuristic. Timing constraint paths may be marked as “constrained” to prevent these paths from being cut. With the cycles and timing constraint paths identified, cuts may be selected that cut the identified timing cycles while preserving the timing constraint paths. The cycle cuts allow the circuit design to be correctly processed within a conventional CAD tool design flow.

Claims22

Dependent claims

A method for circuit design cycle cutting using timing path analysis, the method comprising:

using a computing device to perform the steps of:
accessing a circuit design comprising a plurality of elements interconnected by a plurality of edges, the circuit design further comprising timing constraints;
identifying cycles in the circuit design;
selecting a cycle cut to cut an identified cycle in the circuit design, the selection configured to preserve the timing constraints of the circuit design;
and
generating a directive to cause a computer-aided drafting (CAD) tool to implement the selected cut.

3 more elements

Dependencies are inferred from the claim text.

Cycle cutting with timing path analysis

Life of this patent

Cycle cutting with timing path analysis

Life of this patent

Abstract

Claims22