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US 2013/0097471 A1Published application
Error correction in a stacked memory
AssigneeMicron Technology, Inc.
InventorJoe M. Jeddeloh
Life of this patent
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Abstract
Electronic apparatus, systems, and methods to construct and operate the electronic apparatus and/or systems include a stack of memory dies with user data and/or first level error correction data stored in a stripe across the memory dies. One such stack can include a second level error correction vault, such as a parity vault, to store parity data corresponding to the user data and/or first level error correction data. Additional apparatus, systems, and methods are disclosed.
Claims20
An apparatus comprising:
- a stack of memory dies partitioned into a plurality of data vaults, the stack arranged to store user data in a stripe across the data vaults;
- a vault to operatively store second level error correction data corresponding to the user data;
- and
- a logic die operatively coupled to the stack of memory dies, the logic die structured to control management of allocation of data vaults to the stripe.
1 more element
An apparatus comprising:
- a stack of memory dies partitioned into a plurality of vaults;
- and
- a logic die operatively coupled to the stack of memory dies, the logic die structured to control:
- allocation of portions of a number of vaults of the plurality of vaults to a stripe such that the stripe includes vaults selected as data vaults to store user data in the stripe;
- selection of a vault of the plurality of vaults to operate as a second level error correction vault, as part of the stripe, to operatively store second level error correction data corresponding to the user data;
- determination of whether the plurality of vaults includes a spare vault, based on the allocation of data vaults;
- and
- operation of the spare vault, based on the determination.
5 more elements
Dependencies are inferred from the claim text.