Method and system for implementing interconnection fault tolerance between cpu

A method for implementing fault tolerance in a system,

• providing a system that comprises a first CPU, a second CPU, a first CPU interconnect device, and a second CPU interconnect device, wherein the first CPU interconnect device comprises a first quick path interconnect (QPI) interface and a first serial deserial (SerDes) interface that are connected to each other, the second CPU interconnect device comprises a second QPI interface and a second SerDes interface that are connected to each other, wherein
• the first CPU and the second CPU implement an interconnection through a first connection link, a second connection link and a third connection link;
• the first connection link is established between a QPI interface of the first CPU and the first QPI interface to transmit data sent or received by the first CPU;
• the third connection link is established between a QPI interface of the second CPU and the second QPI interface to transmit data sent or received by the second CPU;
• the second connection link is established between the first SerDes interface and the second SerDes interface to transmit data between the first CPU and the second CPU;
• wherein a fourth data channel is additionally established between the first SerDes interface and the second SerDes interface, the fourth data channel is configured to transmit link state and a link control signal,
• monitoring a link state of any one of the first connection link, the second connection link and the third connection link;
• transmiting a link state through the fourth data channel between the first CPU interconnect device and the second CPU interconnect device;
• and
• recovering any faulty connection links when determining whether any one of the first connection link, the second connection link and the third connection link is faulty.