Computer apparatus and resetting method for real time clock thereof

A computer apparatus comprising:

• an embedded controller for generating a judging result by determining whether the computer apparatus is in an S5 state and determining whether a plurality of pre-determined keys are simultaneously pressed, the embedded controller pulling down a resume reset signal according to the judging result and correspondingly pulling down an operating voltage, the embedded controller pulling down an S5 enabling signal after pulling down the operating voltage for a pre-determined delay time, the embedded controller generating an enabling voltage and a control signal after pulling down the S5 enabling signal;
• and
• a switch coupled to the embedded controller, a first end of the switch receiving the enabling voltage, a control end of the switch receiving the control signal, the switch generating the real time clock reset signal at a second end of the switch according to the control signal.