Memory unit, information processing device, and method
AssigneeFreescale Semiconductor, Inc.
InventorsMichael Priel, Joseph Rabinowicz, Anton Rozen
Life of this patent
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Abstract
A memory unit comprises at least two volatile memory elements, analyzing circuitry and power gate. The memory elements may for example be latches, flip-flops, or registers. Each of the memory elements has at least two different states including a predefined reset state. The analyzing circuitry generates a power-down enable signal in response to each of the memory elements being in its reset state. The power gate powers down the memory elements in response to the power-down enable signal. The memory elements may be arranged to assume their reset states upon powering up the memory unit.
Claims18
A memory unit comprising:
- at least two volatile memory elements, wherein each memory element has having at least two different states including a predefined reset state;
- analyzing circuitry arranged to generate a power-down enable signal in response to each of said memory elements being in its reset state;
- and
- a power gate arranged to power down the memory elements in response to the power-down enable signal.
A method of operating a memory unit, the memory unit comprising at least two volatile memory elements, each of said memory elements having at least two different states including a predefined reset state, the method comprising:
- generating a power-down enable signal in response to each of said memory elements being in its reset state;
- and
- powering down said memory elements in response to the power-down enable signal.
An information processing device comprising:
- a processor;
- and
- a plurality of memory units, coupled to the processor, wherein each memory unit comprises
- a plurality of volatile memory elements wherein each memory element is configured to have a plurality of different states including a predefined reset state,
- analyzing circuitry configured to generate a power-down enable signal in response to each memory element being in the reset state, and
- a power gate configured to power down the memory elements in response to the power-down enable signal.
Dependencies are inferred from the claim text.