Instruction-issuance controlling device and instruction-issuance controlling method
AssigneePanasonic Corporation
InventorTomohiro YAMANA
Life of this patent
Estimating the term…
Abstract
In a multithread processor capable of executing a plurality of threads, in order to select a thread and instruction for increasing a throughput of the multithread processor, an instruction-issuance controlling device included in the multithread processor includes a resource management unit configured to manage stall information indicating whether or not each of threads in execution is in a stalled state; a thread selection unit configured to select a thread which is not in the stalled state among the threads in execution; and an instruction-issuance controlling unit configured to perform controlling so that simultaneously issuable instructions are issued from among the selected thread.
Claims18
An instruction-issuance controlling device included in a multithread processor, the device comprising:
- a resource management unit configured to manage stall information indicating whether or not each of threads in execution is in a stalled state;
- a thread selection unit configured to select a thread which is not in the stalled state among the threads in execution;
- and
- an instruction-issuance controlling unit configured to control the multithread processor so that simultaneously issuable instructions are issued from the selected thread.
A multithread processor comprising:
- an instruction execution unit;
- and
- an instruction-issuance controlling device,
- wherein the instruction-issuance controlling device includes:
- a resource management unit configured to manage stall information indicating whether or not each of threads in execution is in a stalled state;
- a thread selection unit configured to select a thread which is not in the stalled state among the threads in execution;
- and
- an instruction-issuance controlling unit configured to perform controlling so that simultaneously issuable instructions are issued from the selected thread to the instruction execution unit.
A simultaneous multithreading (SMT) multithread processor by which a plurality of instruction groups are simultaneously issued to an instruction execution unit, the SMT multithread processor comprising
- an instruction-issuance controlling device including:
- a resource management unit configured to manage stall information indicating whether or not each of threads in execution is in a stalled state;
- a thread selection unit configured to select threads which are not in the stalled state from among the threads in execution;
- and
- an instruction grouping unit configured to perform controlling so that a plurality of instruction groups, each of which belongs to a corresponding one of the selected threads, are simultaneously issued to the instruction execution unit.
An instruction-issuance controlling method for use in a multithread processor, comprising:
- managing stall information indicating whether or not each of threads in execution is in a stalled state;
- selecting a thread which is not in the stalled state from among the threads in execution;
- and
- performing controlling so that simultaneously issuable instructions are issued from among the selected thread.
Dependencies are inferred from the claim text.