Address Mapping in Memory Systems

A memory system comprising:

• an address mapping circuit to receive an input memory address comprising a first set of address bits, the address mapping circuit applying one of a plurality of logic functions to the input memory address to generate a mapped memory address, at least one of the plurality of logic functions using at least a subset of the first set of address bits in two separate operations that respectively determine first and second portions of the mapped memory address, wherein the plurality of logic functions provide different one-to-one mappings from the input memory address to the mapped memory address;
• and
• a hot region guard mechanism to indicate to the address mapping circuit which of the plurality of logic functions to apply to the input memory address to generate the mapped memory address, wherein the hot region guard mechanism tracks statistics representing a number of write requests and a number of unique regions written to based on the write requests.

A memory device comprising:

• an address mapping circuit to receive an input memory address comprising a first set of address bits, the address mapping circuit applying a logic function to the input memory address to generate a mapped memory address, the logic function using at least a subset of the first set of address bits in two separate operations that respectively determine first and second portions of the mapped memory address.