Back to results
US 2013/0097401 A1Published application
Memory manager
AssigneeSTMicroelectronics (R&D) Ltd.
InventorDavide Sarta
Life of this patent
Estimating the term…
Abstract
A memory management device including a plurality of outputs, each output configured to interface to respective one of a plurality of memories; and a controller configured to cause each buffer allocated to the memories to be divided up substantially equally between each of the plurality of memories.
Claims14
A memory management device comprising:
- a plurality of outputs, each output configured to interface to respective one of a plurality of memories;
- and
- a controller configured to cause each buffer allocated to said memories to be divided up substantially equally between each of said plurality of memories.
Dependencies are inferred from the claim text.