Memory control device, memory control method, data processing device, and image processing system

A memory control method that transfers data from an external memory to a data processing unit having a plurality of processing mechanisms, the memory control method comprising:

• storing an absolute address serving as a common reference value in a given data transfer period;
• storing a plurality of differential addresses therein;
• selecting any one of the plurality of differential addresses in a given order;
• combining the selected differential address with the absolute address to generate a memory address;
• and
• inputting the generated memory address to the external memory, reading the data from the memory address, and transferring the data to the data processing unit.

A data processing device, comprising:

• a data processing unit having a plurality of processing mechanisms in which a plurality of processing mechanisms each having at least an internal memory and an arithmetic circuit are connected in series;
• a control unit that controls the data processing unit;
• an absolute address storage unit that stores an absolute address serving as a common reference value in a given data transfer period;
• a differential address storage unit that stores a plurality of differential addresses therein;
• a differential address selection unit that selects any one of the plurality of differential addresses in a given order;
• a memory address generation unit that combines any differential address selected by the differential address selection unit with the absolute address to generate a memory address;
• and
• a data transfer unit that inputs the memory address generated by the memory address generation unit to the external memory, reads the data from the memory address, and transfers the data to the data processing unit.

A semiconductor integrated circuit, comprising:

• a first register that stores an absolute address serving as a common reference value in a given data transfer period therein;
• a second register that stores a plurality of differential addresses therein;
• a pointer register that designates the plurality of differential addresses in a given order;
• a memory address generator circuit that combines any differential address selected by the pointer register with the absolute address to generate a memory address;
• and
• a data transfer circuit that inputs the memory address generated by the memory address generator circuit to a memory, and reads and transfers the data from the memory address.