Memory controller and methods

A memory controller providing a plurality of read ports that allow shared access to at least one memory device, the memory controller comprising:

• a plurality of read ports, at least one of the read ports having a clock frequency and comprising a data buffer having a plurality of storage locations capable of containing data read from at least one memory device, wherein said read port is configured to respond to a request to read data in the data buffer by reading the data from a first number of said storage locations, and wherein the read port is configured to respond to a request to read data not in the data buffer by reading the data from a first number of said storage locations once the data has been read from the at least one memory device;
• and
• an arbiter having a clock frequency and configured to be able to read at a pre-determined time, data from the at least one memory device on behalf of one of the read ports, and to write the read data into a second number of storage locations of the data buffer of the read port on whose behalf the data was read,
• wherein the second number of storage locations written to by the arbiter, the rate at which the second number of storage locations are written to by the arbiter, the first number of storage locations read by said read port and the rate at which the first number of storage locations of that read port are read provide that the bandwidth of data written to the read port by the arbiter is greater than or equal to the bandwidth of data read by the read port.

A method for providing shared access to at least one memory device via a plurality of write ports, the method comprising:

• receiving, at one of a plurality of write ports, said write port having a clock frequency and comprising a data buffer having a plurality of storage locations, data and writing the received data to at least a first number of storage locations in the data buffer at a pre-determined time;
• and
• reading, at an arbiter having a clock frequency, data from a second number of storage locations of said data buffer at a pre-determined time and writing the data that is read to at least one memory device,
• wherein the second number of storage locations read by the arbiter, the rate at which the second number of storage locations are read by the arbiter, the first number of storage locations written to said write ports and the rate at which the first number of storage locations of said write port are written to provide that the bandwidth of data read from said write port by the arbiter is greater than or equal to the bandwidth of data written to said write port.

A method for providing shared access to at least one memory device via a plurality of read ports, the method comprising:

• responding, at one of a plurality of read ports, said read port having a clock frequency and comprising a data buffer having a plurality of storage locations capable of containing data read from at least one memory device, to a request to read data by:
• when said data is in said data buffer, reading the data from a first number of said storage locations, and
• when said data is not in said data buffer, reading the data from a first number of said storage locations once the data has been read from the at least one memory device;
• and
• reading, at an arbiter having a clock frequency, data from the at least one memory device on behalf of one of the read ports at a pre-determined time, and writing the read data into a second number of storage locations of the data buffer of the read port on whose behalf the data was read,
• wherein the second number of storage locations written to by the arbiter, the rate at which the second number of storage locations are written to by the arbiter, the first number of storage locations read by said read port and the rate at which the first number of storage locations of that read port are read provide that the bandwidth of data written to the read port by the arbiter is greater than or equal to the bandwidth of data read by the read port.