Device and data processing system

A data processing system comprising:

• a memory system comprising a plurality of memory bank groups each including a plurality of memory banks storing data;
• a control system comprising a plurality of processing engines processing the data and a memory controller controlling an access to the memory system from the processing engines, the plurality of processing engines corresponding to the plurality of memory bank groups to be accessed;
• data lines transmitting the data between the memory system and the memory controller;
• and
• a first register storing access data including a plurality of latencies each as a time interval from issuing a command for each of the memory bank groups to staring a data transfer through the data lines, the first register being included in the memory controller,
• wherein each of values of the plurality of latencies is corresponded to a priority order of an access of each of the processing engines,
• and the memory controller controls an order of issuing commands for at least two of the memory bank groups in response to access requests from the processing engines based on the access data including the plurality of latencies.