US 2013/0097387 A1 · MEMORY-BASED APPARATUS AND METHOD

Abstract

Aspects of various embodiments are directed to memory circuits, such as cache memory circuits. In accordance with one or more embodiments, cache-access to data blocks in memory is controlled as follows. In response to a cache miss for a data block having an associated address on a memory access path, data is fetched for storage in the cache (and serving the request), while one or more additional lookups are executed to identify candidate locations to store data. An existing set of data is moved from a target location in the cache to one of the candidate locations, and the address of the one of the candidate locations is associated with the existing set of data. Data in this candidate location may, for example, thus be evicted. The fetched data is stored in the target location and the address of the target location is associated with the fetched data.

Claims20

Dependent claims

An apparatus comprising:

a memory circuit configured and arranged with cache lines that store data blocks;
and
a controller circuit configured and arranged to control cache-access to the data blocks in the memory circuit by, in response to a cache miss for a data block having an associated address on a memory access path,
fetching data for storage in the memory circuit while executing additional lookups on the memory access path to identify a plurality of candidate locations to store data,
moving an existing set of data from a target location in the cache to one of the plurality of candidate locations and associating the address of the one of the plurality of candidate locations with the existing set of data, the one of the plurality of candidate locations corresponding to one of a subset of locations that are accessible via a single lookup, and
storing the fetched data in the target location and associating the address of the target location with the fetched data.

3 more elements

A method for accessing data blocks having an associated address identifying a cache line in a memory circuit, the method comprising:

in response to a cache miss for a data block having an associated address on a memory access path, fetching data for storage in the memory circuit while executing additional lookups on the memory access path to identify a plurality of candidate locations to store data,
moving an existing set of data from a target location in the cache to one of the plurality of candidate locations and associating the address of the one of the plurality of candidate locations with the existing set of data, the one of the plurality of candidate locations corresponding to one of a subset of locations that are accessible via a single lookup, and
storing the fetched data in the target location and associating the address of the target location with the fetched data.

Dependencies are inferred from the claim text.

Memory-based apparatus and method

Life of this patent

Memory-based apparatus and method

Life of this patent

Abstract

Claims20