Cache memory system for tile based rendering and caching method thereof
AssigneesIndustry-Academia Cooperation Group of Sejong University, Samsung Electronics Co., Ltd.
InventorsWon Jong LEE, Sang Oak Woo, Seok Yoon Jung, Woo Chan Park, Young Sik Kim
Life of this patent
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Abstract
A cache memory system and a caching method for a tile-based rendering may be provided. Each of cache lines in the cache memory system may include delayed-replacement information. The delayed-replacement information may indicate whether texture data referred to at a position of an edge of a tile is included in a cache line. When a cache line corresponding to an access-requested address is absent in the cache memory system, the cache memory system may select and remove a cache line to be removed from an associative cache unit, based on delayed-replacement information.
Claims17
A cache memory system, the system comprising:
- a first associative cache unit to simultaneously search for a cache line corresponding to an access-requested address from one or more first cache lines;
- and
- a second associative cache unit to store one or more second cache lines, and to simultaneously search for a cache line corresponding to the access-requested address from the second cache lines,
- wherein the first associative cache unit includes delayed-replacement information for each of the first cache lines, and the first associative cache unit selects and removes one cache line from among the first cache lines based on the delayed-replacement information for the first cache lines when the cache line corresponding to the access-requested address is absent in the first associative cache unit and the second associative cache unit.
A caching method, the method comprising:
- simultaneously searching, by a first associative cache unit, for a cache line corresponding to an access-requested address from among one or more first cache lines, the first associative cache unit including delayed-replacement information for each of the first cache lines;
- simultaneously searching, by a second associative cache unit storing one or more second cache lines, for a cache line corresponding to the access-requested address from second cache lines;
- selecting, by the first associative cache unit, one of the first cache lines, based on delayed-replacement information for the first cache lines when the cache line corresponding to the access-requested address is absent in the first associative cache unit and the second associative cache unit;
- and
- removing, by the first associative cache unit, the selected cache line from the first associative cache unit,
- wherein the first associative cache unit uses the delayed-replacement information for the first cache lines to select one of the first cache lines and to remove the selected cache line.
Dependencies are inferred from the claim text.