Multi-core processor system, cache coherency control method, and computer product

A cache coherency control method executed by a first core among a plurality of cores capable of controlling a cache coherency mechanism that establishes coherency among shared data values stored in a cache memory accessed by each of the cores, the cache coherency control method comprising:

• detecting a first thread executed by the first core;
• identifying, when at the detecting the first thread is detected, a second thread under execution by a second core other than the first core and among the cores;
• determining whether shared data commonly accessed by the first thread and the second thread is present;
• and
• causing, when at the determining no shared data commonly accessed is determined to be present, establishment of coherency for a first cache memory corresponding to the first core and a second cache memory corresponding to the second core, to stop.

A computer-readable recording medium storing a program that causes a first core among a plurality of cores capable of controlling a cache coherency mechanism that establishes coherency among shared data values stored in a cache memory accessed by each of the cores, to execute a cache coherency control process comprising:

• detecting a first thread executed by the first core;
• identifying, when at the detecting the first thread is detected, a second thread under execution by a second core other than the first core and among the cores;
• determining whether shared data commonly accessed by the first thread and the second thread is present;
• and
• causing, when at the determining no shared data commonly accessed is determined to be present, establishment of coherency for a first cache memory corresponding to the first core and a second cache memory corresponding to the second core, to stop.