Multi-core processor system, computer product, and control method
AssigneeFujitsu Limited
InventorsKoji Kurihara, Koichiro Yamashita, Hiromasa Yamauchi
Life of this patent
Estimating the term…
Abstract
A multi-core processor system includes a first processor that among cores of the multi-core processor, identifies other cores having a cache miss-hit rate lower than that of a given core storing a specific program in a cache, based on a task information volume of each core; a control circuit that migrates the specific program from the cache of the given core to a cache of the identified core; and a second processor that, after the specific program is migrated to the cache of the identified core, sets as a write-inhibit area, an area that is of the cache of the identified core and to which the specific program is stored.
Claims3
A multi-core processor system comprising:
- a first processor that among cores of the multi-core processor, identifies other cores having a cache miss-hit rate lower than that of a given core storing a specific program in a cache, based on a task information volume of each core;
- a control circuit that migrates the specific program from the cache of the given core to a cache of the identified core;
- and
- a second processor that, after the specific program is migrated to the cache of the identified core, sets as a write-inhibit area, an area that is of the cache of the identified core and to which the specific program is stored.
A computer-readable recording medium stores a control program causing a multi-core processor capable of accessing a control circuit that upon receiving a migration notification of a cache of a destination core, a cache of a source core and a program to be migrated, migrates the program from the cache of the source core to the cache of the destination core, to execute a process comprising:
- identifying among cores of the multi-core processor, other cores having a cache miss-hit rate lower than that of a given core storing a specific program in a cache, based on a task information volume of each core;
- causing the control circuit to migrate the specific program from the cache of the given core to a cache of the identified core;
- and
- setting as a write-inhibit area and after the specific program is migrated to the cache of the identified core, an area that is of the cache of the identified core and to which the specific program is stored.
A control method executed by a multi-core processor capable of accessing a control circuit that upon receiving a migration notification of a cache of a destination core, a cache of a source core and a program to be migrated, migrates the program from the cache of the source core to the cache of the destination core, the control method comprising:
- identifying among cores of the multi-core processor, other cores having a cache miss-hit rate lower than that of a given core storing a specific program in a cache, based on a task information volume of each core;
- causing the control circuit to migrate the specific program from the cache of the given core to a cache of the identified core;
- and
- setting as a write-inhibit area and after the specific program is migrated to the cache of the identified core, an area that is of the cache of the identified core and to which the specific program is stored.
Dependencies are inferred from the claim text.