US 2013/0097363 A1 · MEMORY CONTROL DEVICE

Abstract

A memory control device for controlling a primary controller and a secondary controller to access a flash memory is provided. A bus switch is coupled to the primary controller, the secondary controller and the flash memory via a first, second and third serial peripheral interface (SPI) buses, respectively. A selecting unit selectively couples the third SPI bus to one of the first and second buses. When the bus switch receives an access request from the primary controller via the first SPI bus, the selecting unit couples the third SPI bus to the first SPI bus, so as to transmit a chip select signal, a clock signal and a master output slave input (MOSI) signal from the primary controller to the flash memory for accessing the flash memory. The first access request is provided by the first chip select signal.

Claims20

Dependent claims

A memory control device for controlling a primary controller and a secondary controller to access a flash memory, comprising:

a bus switch coupled to the primary controller, the secondary controller and the flash memory via a first, second and third serial peripheral interface (SPI) buses, respectively, comprising:
a selecting unit, selectively coupling the third SPI bus to one of the first and second buses,
wherein when the bus switch receives a first access request from the primary controller via the first SPI bus, the selecting unit couples the third SPI bus to the first SPI bus, so as to transmit a first chip select signal, a first clock signal and a first master output slave input (MOSI) signal from the primary controller to the flash memory for accessing the flash memory, wherein the first access request is provided by the first chip select signal.

Dependencies are inferred from the claim text.

Memory control device

Life of this patent

Memory control device

Life of this patent

Abstract

Claims20