System and Method for High-Performance, Low-Power Data Center Interconnect Fabric
AssigneeCalxeda, Inc.
InventorsMark Bradley Davis, David James Borland
Life of this patent
Estimating the term…
Abstract
A system and method are provided that support a routing using a tree-like or graph topology that supports multiple links per node, where each link is designated as an Up, Down, or Lateral link, or both, within the topology. The system may use a segmented MAC architecture which may have a method of re-purposing MAC IP addresses for inside MACs and outside MACs, and leveraging what would normally be the physical signaling for the MAC to feed into the switch.
Claims21
A system on a chip, comprising:
- one or more processing cores;
- one or more management processors coupled to each one of the one or more processing cores;
- one or more communication interfaces;
- and
- one or more interrupt controllers coupled between each one of the one or more processing cores and the one or more management processors for enabling an interrupt transmitted for reception by a first one of the one or more processing cores to be reflected to the one or more management processors from the first one of the one or more processing cores while the first one of the one or more processing cores is in the inactive state.
The system on a chip of claim I wherein the one or more management processors cause the interrupt to be provided to the first one of the one or more processing cores in response to the first one of the one or more processing cores being transitioned from the inactive state to an active state.
A computing system, comprising:
- one or more server on a chip units each having one or more processing cores and one or more power management portions coupled between each one of the one or more processing cores one or more processing cores;
- one or more interconnect portions couple to each one of the one or more server on a chip units for enabling the computing system to be communicatively connected to one or more other computing systems;
- and
- one or more interrupt controllers coupled between each one of the one or more processing cores and the one or more power management portions for enabling an interrupt transmitted for reception by a first one of the one or more processing cores to be reflected to the one or more management processors from the first one of the one or more processing cores while the first one of the one or more processing cores is in the inactive state,
A computing system, comprising:
- one or more server on a chip units each having one or more processing cores and one or more power management portions coupled between each one of the one or more processing cores one or more processing cores;
- one or more interconnect portions couple to each one of the one or more server on a chip units for enabling the computing system to be communicatively connected to one or more other computing systems;
- one or more interrupt controllers coupled between each one of the one or more processing cores and the one or more power management portions for enabling an interrupt transmitted for reception by a first one of the one or more processing cores to be reflected to the one or more management processors from the first one of the one or more processing cores while the first one of the one or more processing cores is in the inactive state
- operating system software accessible by each one of the one or more processing cores of the one or more server on a chip units;
- and
- a first memory structure coupled to one or more direct memory access portions of each one of the one or more server on a chip units for providing direct access memory functionality within the computing system.
Dependencies are inferred from the claim text.