Methods of manufacturing a vertical type semiconductor device

A method of forming an integrated wiring comprising:

• alternately integrating first to n-th insulating interlayers and first to n-th contact forming layers on a substrate;
• forming an upper insulating interlayer on an n-th contact forming layer of the first to n-th contact forming layers;
• partially etching the upper insulating interlayer to form an upper insulating interlayer pattern that defines initial and preliminary contact holes;
• forming a first reflection limiting layer pattern and a first photoresist pattern on the upper insulating layer for covering inlet portions of the initial and preliminary contact holes while selectively exposing first preliminary contact holes at first positions from edge portions of the upper insulating interlayer pattern;
• performing a first etching of one of the first to n-th insulating interlayers and first to n-th contact forming layers exposed through the first preliminary contact holes to expose a contact forming layer at a lower position than a bottom portion of the first preliminary contact hole;
• partially removing sidewalls of the first photoresist pattern and the first reflection limiting layer pattern to form a second reflection limiting layer pattern and a second photoresist pattern,
• the second photoresist and reflection limiting patterns exposing first and second preliminary contact holes at first and second positions from the edge portions of the upper insulating interlayer pattern;
• performing a second etching with respect to layers exposed through the first and second preliminary contact holes to expose the contact forming layers respectively provided at a lower position than the bottom portion of the first and second preliminary contact holes,
• the contact holes having depths decreasing from the edge portion to a center portion of the;
• forming an insulating spacer on the sidewalls of the contact holes;
• and
• filling up a conductive material in the contact holes including the insulating spacer to form contacts.

A method of manufacturing a semiconductor device comprising:

• forming 1 to n-th first and second layer patterns alternatingly stacked,
• n being an integer greater than or equal to 3;
• forming a mask pattern on the n-th second layer pattern of the 1 to n-th second layer patterns,
• the mask pattern defining 1 to n-th openings spaced apart in a horizontal direction over a first portion of the n-th second layer pattern;
• forming a first multilayer pattern on the mask pattern,
• the first multilayer pattern including a first resist pattern on a first reflection limiting pattern,
• the first multilayer pattern exposing one of the 1 to n-th openings of the mask pattern;
• forming 1 to n-th contact holes having different depths through the 1 to n-th openings by,
• (A) etching at least one of the 1 to n-th first and second layer patterns using the mask pattern and the first multilayer pattern as an etch mask and at least one of the 1 to (n−1)-th second layer patterns as an etch stop,
• (B) laterally removing part of the first multilayer pattern to expose another opening of the 1 to n-th openings of the mask pattern,
• (C) repeating (A) and (B) until 1 to (n−1)-th contact holes are formed, and
• (D) removing a remaining portion of the first multilayer pattern to expose the n-th opening as the n-th contact hole;
• and
• forming contacts by filling the 1 to n-th contact holes with a conductive material.