Technique for reducing topography-related irregularities during the patterning of a dielectric material in a contact level of closely spaced transistors
AssigneeAdvanced Micro Devices, Inc.
InventorsRalf Richter, Heike Salz, Robert Seidel
Life of this patent
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Abstract
In a dual stress liner approach, the surface conditions after the patterning of a first stress-inducing layer may be enhanced by appropriately designing an etch sequence for substantially completely removing an etch stop material, which may be used for the patterning of the second stress-inducing dielectric material, while, in other cases, the etch stop material may be selectively formed after the patterning of the first stress-inducing dielectric material. Hence, the dual stress liner approach may be efficiently applied to semiconductor devices of the 45 nm technology and beyond.
Claims23
-9. (canceled)
A method, comprising:
- forming a layer stack above first and second conductive lines formed in a device level of a semiconductor device, said layer stack comprising a first stress-inducing dielectric layer and an etch stop layer formed above said first stress-inducing dielectric layer;
- forming a mask so as to expose said second conductive lines and cover said first conductive lines;
- performing an etch sequence to remove said first stress-inducing dielectric layer and said etch stop layer from above said second conductive lines and reduce a width of sidewall spacer elements formed on sidewalls of said second conductive lines, wherein reducing said width comprises removing a first thickness portion of said sidewall spacer elements while leaving a second thickness portion of said sidewall spacer elements adjacent to said sidewalls;
- after performing said etch sequence, forming a second stress-inducing dielectric layer above said second conductive lines and on a portion of said etch stop layer located above said first conductive lines;
- and
- selectively removing said second stress-inducing dielectric layer from above said first conductive lines by using said etch stop layer as an etch stop.
-24. (canceled)
A method, comprising:
- forming first and second conductive lines in a device level of a semiconductor device, at least a portion of each of said first and second conductive lines extending above an isolation structure of said semiconductor device;
- forming a layer stack above said first and second conductive lines, said layer stack comprising a first stress-inducing layer and an etch stop layer formed above said first stress-inducing layer;
- forming a patterned etch mask above said semiconductor device, said patterned etch mask exposing said second conductive lines and covering said first conductive lines;
- performing an etch sequence to remove said first stress-inducing layer and said etch stop layer from above said second conductive lines and to reduce a width of sidewall spacer elements formed on sidewalls of said second conductive lines, wherein reducing said width comprises removing a first thickness portion of said sidewall spacer elements while leaving a second thickness portion of said sidewall spacer elements adjacent to said sidewalls;
- after performing said etch sequence, forming a second stress-inducing layer above said semiconductor device, said second stress-inducing layer covering said first and second conductive lines and having an opposite type of stress from said first stress-inducing layer;
- and
- selectively removing said second stress-inducing layer from above said first conductive lines.
Dependencies are inferred from the claim text.