Memory array with surrounding gate access transistors and capacitors with global and staggered local bit lines
AssigneeMicron Technology, Inc.
InventorLeonard Forbes
Life of this patent
Estimating the term…
Abstract
A memory array with staggered local data/bit lines extending generally in a first direction formed in an upper surface of a substrate and memory cell access transistors extending generally upward and aligned generally atop a corresponding local data/bit line. Selected columns of the memory cell access transistors are sacrificed to define local data/bit access transistors which are interconnected with overlying low resistance global data/bit lines. The global data/bit lines provide selectable low resistance paths between memory cells and sense amplifiers. The sacrificed memory cell access transistors and staggered local data/bit lines provide increased footprints for sense amplifiers to facilitate increased circuit integration.
Claims20
A method of fabricating a memory array, the method comprising:
- forming sidewall structures arranged against inner surfaces of openings in sidewall material, the openings being aligned generally with first data/bit lines;
- forming vertical extensions within holes in the sidewall structures, the vertical extensions being generally aligned on top of corresponding first data/bit lines;
- and
- forming second data/bit lines extending across and above the vertical extensions and being generally arranged parallel to the first data/bit lines.
A method of fabricating a memory array, the method comprising:
- forming sidewall structures arranged against inner surfaces of openings in sidewall material, the openings being aligned generally with first data/bit lines;
- forming vertical extensions within holes in the sidewall structures, the vertical extensions being aligned generally with the first data/bit lines;
- and
- forming second data/bit lines extending across the vertical extensions, wherein gate conductors formed about the vertical extensions are arranged with respect to word lines such that the gate conductor is in electrical contact with a respective word line along a first contact surface and along a second contact surface which is arranged substantially opposite the first contact surface.
A method of fabricating a memory array, the method comprising:
- providing a semiconductor substrate;
- forming sidewall structures arranged against inner surfaces of openings in sidewall material, the openings being aligned generally with first data/bit lines;
- forming vertical extensions within holes in the sidewall structures, the vertical extensions being aligned generally with the first data/bit lines;
- and
- forming second data/bit lines extending across the vertical extensions;
- wherein gate conductors formed about the vertical extensions are arranged with respect to word lines such that the gate conductor is in electrical contact with a respective word line along a first contact surface and along a second contact surface which is arranged substantially opposite the first contact surface.
Dependencies are inferred from the claim text.