Method for fabricating nonvolatile memory device

A method for fabricating a nonvolatile memory device, comprising:

• forming a first insulation layer for a tunnel insulation layer and a first conductive layer for a floating gate on a substrate including a cell region, a first peripheral circuit region, and a second peripheral circuit region;
• forming a first isolation trench in the cell region by selectively etching the first conductive layer, the first insulation layer, and the substrate of the cell region;
• forming a first isolation layer filled in the first isolation trench;
• forming a second insulation layer for a charge blocking layer and a conductive capping layer on the first isolation layer and the first conductive layer;
• removing the capping layer and the second insulation layer of the first peripheral circuit region, while patterning the capping layer and the second insulation layer of the second peripheral circuit region to be positioned in an active region;
• is forming a second conductive layer for a control gate on a resultant structure;
• and
• forming first gate patterns by selectively etching the second conductive layer, the capping layer, the second insulation layer, the first conductive layer, and the first insulation layer of the cell region, and forming a second isolation trench in the first and second peripheral circuit regions by selectively etching the second conductive layer, the first conductive layer, the first insulation layer, and the substrate of the first and second peripheral circuit regions.

A method for fabricating a nonvolatile memory device, comprising:

• forming a first insulation layer and a first conductive layer on a substrate including a first region and a second region;
• forming a first isolation layer in the substrate of the first regions;
• forming a second insulation layer and a conductive capping layer on the first isolation layer and the first conductive layer;
• etching the capping layer and the second insulation layer of the second region;
• forming a second conductive layer on a resultant structure;
• and
• forming first gate patterns in the first region and a second isolation trench in the second regions by selectively etching the second conductive layer, the capping layer, the second insulation layer, the first conductive layer, and the first insulation layer of the first region and the second conductive layer, the first conductive layer, the first insulation layer, and the substrate of the second region.