Methods of forming highly scaled semiconductor devices using a disposable spacer technique

A method, comprising:

• forming gate structures for a PMOS transistor and for an NMOS transistor above a semiconducting substrate, said gates structures being adjacent to one another;
• forming a first liner layer above said substrate and above said gate structures for both said PMOS transistor and said NMOS transistor;
• after forming said first liner layer:
• performing a plurality of extension ion implant processes through said first liner layer to form extension implant regions in said substrate for said PMOS transistor and said NMOS transistor;
• and
• performing a plurality of halo ion implant processes through said first liner layer to form halo implant regions in said substrate for said PMOS transistor and said NMOS transistor;
• after forming said extension implant regions and said halo implant regions, removing said first liner layer;
• forming a second liner layer above said substrate and above said gate structures for both said PMOS transistor and said NMOS transistor;
• forming a first spacer on said second liner layer proximate said gate structures of both said PMOS transistor and said NMOS transistor;
• performing a plurality of source/drain ion implant processes with said first spacer in place to form deep source/drain implant regions in said substrate for said PMOS transistor and said NMOS transistor;
• removing first spacer leaving said second liner layer in place;
• and
• after removing said first spacer, forming a layer of material between said adjacent gate structures, wherein said layer of material occupies at least the space formerly occupied by said first spacer.

A method, comprising:

• forming gate structures for a PMOS transistor and for an NMOS transistor above a semiconducting substrate, said gates structures being adjacent to one another;
• forming a continuous liner layer that extends continuously above said substrate and above said gate structures for both said PMOS transistor and said NMOS transistor;
• after forming said continuous liner layer:
• performing a plurality of extension ion implant processes to form extension implant regions in said substrate for said PMOS transistor and said NMOS transistor;
• and
• performing a plurality of halo ion implant processes form halo implant regions in said substrate for said PMOS transistor and said NMOS transistor;
• after forming said extension implant regions and said halo implant regions, removing said continuous liner layer, and thereafter forming an encapsulating layer above said substrate and above said gate structures for both said PMOS transistor and said NMOS transistor;
• forming a first spacer adjacent to said encapsulating layer and proximate said gate structures of both said PMOS transistor and said NMOS transistor;
• performing a plurality of source/drain ion implant processes with said first spacer in place to form deep source/drain implant regions in said substrate for said PMOS transistor and said NMOS transistor;
• and
• after forming said deep source/drain implant regions, removing first spacer.