System and Method for High-Performance, Low-Power Data Center Interconnect Fabric
AssigneeCalxeda, Inc.
InventorsMark Bradley Davis, David James Borland
Life of this patent
Estimating the term…
Abstract
A system and method are provided that support a routing using a tree-like or graph topology that supports multiple links per node, where each link is designated as an Up, Down, or Lateral link, or both, within the topology. The system may use a segmented MAC architecture which may have a method of re-purposing MAC IP addresses for inside MACs and outside MACs, and leveraging what would normally be the physical signaling for the MAC to feed into the switch.
Claims20
A system on a chip configured for providing server functionality to one or more computing systems, comprising:
- one or more processing cores;
- one or more peripheral element interfaces coupled to the one or more processing cores;
- and
- one or more management processors coupled to each one of the one or more processing cores.
The system on a chip of claim 23 wherein:
- the one or more management processors assess the second one of the one or more processing cores to determine an available processing power capacity prior to causes the communication request to be delivered to the second one of the one or more processing cores;
- and
- the one or more management processors cause the communication request to be delivered to the second one of the one or more processing cores in response to determining that the second one of the one or more processing cores has sufficient processing power available for performing the task to be initiated by the communication request.
A system on a chip configured for providing server functionality to one or more computing systems, comprising:
- one or more processing cores;
- one or more peripheral element interfaces coupled to the one or more processing cores;
- one or more external ports for allowing communication of information between the one or more processing cores and the one or more computing system;
- a switching fabric coupled between each one of the one or more peripheral element interfaces and each one of the one or more external ports;
- and
- one or more management processors coupled to the fabric switch and to each one of the one or more processing cores.
The system on a chip of claim 15 wherein the one or more management processors cause a communication request directed to a first one of the one or more processing cores to be held in the switching fabric while the first one of the one or more processing cores is in an inactive state and causes the communication request to be received by the first one of the one or more processing cores in response to the first one of the one or more processing cores being transitioned from the inactive state to an active state.
The system on a chip of claim 18 wherein:
- the one or more management processors assess the second one of the one or more processing cores to determine an available processing power capacity prior to causes the communication request to be delivered to the second one of the one or more processing cores;
- and
- the one or more management processors cause the communication request to be delivered to the second one of the one or more processing cores in response to determining that the second one of the one or more processing cores has sufficient processing power available for performing the task to be initiated by the communication request.
Dependencies are inferred from the claim text.