Energy Efficient Processor Having Heterogeneous Cache
AssigneeWisconsin Alumni Research Foundation
InventorsNam Sung Kim, Stark C. Draper
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Abstract
A heterogeneous cache structure provides several memory cells into different ways each associated with different minimum voltages below which the memory cells produce substantial state errors. Reduced voltage operation of the cache may be accompanied by deactivating different ways according to the voltage reduction. The differentiation between the memory cells in the ways may be implemented by devoting different amounts of integrated circuit area to each memory cell either by changing the size of the transistors comprising the memory cell or devoting additional transistors to each memory cell in the form of shared error correcting codes or backup memory cells.
Claims19
A cache system comprising a series of addressable transistor memory cells holding digital data when powered by an operating voltage,
- wherein the addressable transistor memory cells are grouped into at least two portions that may be independently deactivated,
- wherein the portions provide different architectures having different predetermined susceptibility to errors as a function of operating voltage whereby individual portions may be deactivated or activated with changes in operating voltage according to the predetermined susceptibility to errors as a function of operating voltage.
An integrated circuit adapted to communicate with a main memory and comprising:
- a processor;
- a cache memory providing multiple independently controlled groups of memory cells, wherein the groups of memory cells have predetermined differing susceptibility to reduction in operating voltage;
- and
- a cache controller communicating with the cache memory to:
- (a) monitor an operating state of the integrated circuit to deduce an operating voltage;
- and
- (b) selectively activate and deactivate groups of memory cells as a function of operating voltage according to the predetermined differing susceptibility to operating voltage induced error of the groups.
A method of memory management in an integrated circuit of the type including a processor and a cache memory providing multiple independently controlled groups of memory cells, wherein the groups of memory cells have predetermined differing susceptibility to reduction in operating voltage, the method comprising the steps of:
- (a) monitoring an operating state of the integrated circuit to deduce an operating voltage;
- and
- (b) selectively activating and deactivating groups of memory cells as a function of operating voltage according to the predetermined differing susceptibility to reduction in operating voltage of the groups.
Dependencies are inferred from the claim text.