Negative word line driver for semiconductor memories
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChen-Lin Yang, Wei Min Chan, Chung-Hsien Hua
Life of this patent
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Abstract
A semiconductor memory includes a word line driver and a negative voltage generator. The word line driver includes a first inverter configured to drive a word line at one of a first voltage supplied by a first voltage source and a second voltage supplied by a second voltage source. The negative voltage generator is configured to provide a negative voltage with respect to the second voltage to an input of the first inverter in response to a control signal for performing at least one of a read or a write operation of a memory bit cell coupled to the word line.
Claims20
A semiconductor memory, comprising:
- a word line driver including a first inverter configured to drive a word line at one of a first voltage supplied by a first voltage source and a second voltage supplied by a second voltage source;
- and
- a negative voltage generator configured to provide a negative voltage with respect to the second voltage to an input of the first inverter in response to a control signal for performing at least one of a read or a write operation of a memory bit cell coupled to the word line.
A semiconductor memory, comprising:
- a plurality of word lines each coupled to a respective plurality of bit cells;
- at least one word line driver coupled to at least one of the plurality of word lines, the at least one word line driver including a first inverter configured to drive the at least one word line at one of a first voltage supplied by a first voltage source and a second voltage supplied by a second voltage source;
- and
- at least one negative voltage generator configured to provide a negative voltage with respect to the second voltage to an input of the first inverter in response to a control signal for performing at least one of a read or a write operation of a memory bit cell coupled to the at least one of the plurality of word lines.
A semiconductor memory, comprising:
- a plurality of word lines each coupled to a respective plurality of bit cells;
- at least one word line driver coupled to at least one of the plurality of word lines, the at least one word line driver including a first inverter configured to drive the at least one word line at one of a first voltage supplied by a first voltage source and a second voltage supplied by a second voltage source;
- and
- at least one negative voltage generator configured to provide a negative voltage with respect to the second voltage to an input of the first inverter in response to a control signal for performing at least one of a read or a write operation of a memory bit cell coupled to the at least one of the plurality of word lines, the at least one negative voltage generator including:
- a timing device having an input coupled to a first node that is coupled to the input of the first inverter and having an output coupled to a second node;
- a first transistor having a gate coupled to the second node, a source coupled to the second voltage supply, and a drain coupled to a third node;
- and
- a capacitor coupled to the second node and to the third node and configured to generate the negative voltage in response to the control signal.
Dependencies are inferred from the claim text.