Integrated circuit comprising a non-dedicated terminal for receiving an erase program high voltage
AssigneeSTMicroelectronics (Rousset) SAS
InventorFrancois Tailliet
Life of this patent
Estimating the term…
Abstract
The disclosure relates to an integrated circuit electrically powered by a supply voltage and comprising a memory electrically erasable and/or programmable by means of a second voltage greater than the supply voltage. The integrated circuit comprises means for receiving the second voltage by the intermediary of a reception terminal of the supply voltage or by the intermediary of a reception or emission terminal of a data or clock signal. Applicable in particular to electronic tags comprising a reduced number of interconnection terminals.
Claims18
An electronic system, comprising:
- an integrated memory circuit implemented on a semiconductor chip, the memory circuit including:
- a first terminal configured to receive a supply voltage from off of the chip;
- a second terminal configured to receive from off of the chip at least one of a data signal and a clock signal;
- and
- a memory configured to receive the supply voltage and to be modified electrically by a modify voltage greater than the supply voltage, and
- a data bus coupled to the integrated memory circuit configured to apply the modify voltage to the integrated memory circuit via at least one of the first and second terminals.
A method, comprising:
- writing data in an integrated memory circuit implemented in a semiconductor chip and electrically powered by a supply voltage, the integrated memory circuit including a memory modifiable electrically by a modify voltage greater than the supply voltage, and a terminal configured to receive at least one of the supply voltage, a data signal, and a clock signal, the writing including:
- applying a write command to the integrated memory circuit;
- and
- supplying the modify voltage to the terminal of the integrated memory circuit.
An electronic system, comprising:
- an integrated memory circuit implemented on a semiconductor chip, the integrated memory circuit including:
- a first terminal configured to receive a supply voltage from off of the chip;
- a second terminal configured to receive from off of the chip at least one of a data signal and a clock signal;
- and
- a memory configured to receive the supply voltage and to be modified electrically by a modify voltage greater than the supply voltage;
- and
- a voltage management device coupled to a data bus and configured to:
- monitor communications upon the data bus and detect that a write command is directed to the integrated memory circuit, and
- transmit the modify voltage to the first integrated memory device in response to detecting the write command.
Dependencies are inferred from the claim text.