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US 2013/0094303 A1Published application
Complementary Reference Method for High Reliability Trap-Type Non-Volatile Memory
AssigneeHalo LSI, Inc.
InventorsNori Ogura, Tomoko Ogura, Seiki Ogura
Life of this patent
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Abstract
Methods of complementary pairing of memory cells are described. These methods include two physical memory cells in a complementary pair, a complementary pair of reference cells for each erase block, and a physical complementary pair storing multiple data bits.
Claims12
A method of complementary pairing of memory cells comprising:
- providing a set of at least two reference cells per erase block wherein a first reference cell has a value of ‘1’ and a second reference cell has a value of ‘0’;
- and
- comparing a selected memory cell in said erase block to said two reference cells to determine whether said memory cell has a value of ‘0’ or ‘1’.
A memory cell array comprising:
- an array of insulator or nitride or trap-type storage device memory cells;
- a set of two reference cells per erase block of memory cells wherein a first reference cell has a value of ‘1’ and a second reference cell has a value of ‘0’;
- and
- a comparator comparing a selected memory cell in said erase block to said two reference cells to determine whether said memory cell has a value of ‘0’ or ‘1’.
1 more element
Dependencies are inferred from the claim text.