Back to results
US 2013/0094302 A1Published application
Integrated circuit chip and semiconductor memory device
AssigneeHynix Semiconductor Inc.
InventorChang-Ho Do
Life of this patent
Estimating the term…
Abstract
An integrated circuit chip includes an internal circuit configured to generate output data, an inversion determination unit configured to activate/deactivate an inversion signal according to state information regarding a state of the integrate circuit chip, and a signal output circuit configured to invert or not to invert the output data in response to the inversion signal and output the inverted or non-inverted output data.
Claims23
An integrated circuit chip comprising:
- an internal circuit configured to generate output data;
- an inversion determination unit configured to activate/deactivate an inversion signal according to state information regarding a state of the integrate circuit chip;
- and
- a signal output circuit configured to invert or not to invert the output data in response to the inversion signal and output the inverted or non-inverted output data.
1 more element
A semiconductor memory device comprising:
- a cell array area;
- a plurality of data buses configured to transmit a plurality of data bits outputted from the cell array area;
- a parallel-serial conversion circuit configured to convert parallel data loaded in the plurality of data buses into serial data;
- an inversion determination unit configured to activate/deactivate an inversion signal according to state information regarding a state of the semiconductor memory device;
- and
- a data output circuit configured to invert the serial data outputted from the parallel-serial conversion circuit in response to the inversion signal and output the inverted data to a data pad.
3 more elements
A semiconductor memory device comprising:
- a cell array area;
- a plurality of data buses configured to transmit a plurality of data bits outputted from the cell array area;
- a pipe latch configured to latch parallel data loaded in the plurality of data buses and output parallel data;
- an inversion determination unit configured to activate/deactivate an inversion signal according to state information regarding the state of the semiconductor memory device;
- and
- a parallel data inversion unit configured to invert the parallel data outputted from the pipe latch when the inversion signal is activated, and configured not to invert the parallel data outputted from the pipe latch when the inversion signal is deactivated.
3 more elements
A method for testing a semiconductor memory device, comprising:
- inputting data to a cell array area;
- reading a plurality of data bits stored in the cell array area and loading the read data into a plurality of data buses;
- converting parallel data loaded in the plurality of data buses into serial data;
- activating/deactivating an inversion signal according to state information regarding the state of the semiconductor memory device;
- inverting/non-inverting the serial data in response to the inversion signal;
- and
- outputting the inverted/non-inverted data to a data pad.
4 more elements
Dependencies are inferred from the claim text.