Nonvolatile memory device, programming method of nonvolatile memory device and memory system including nonvolatile memory device

A method of programming a three-dimensional non-volatile memory including bit lines, word lines and a three dimensional array of memory cell transistors comprising a plurality of memory cell transistor strings, each memory cell string including a vertical stack of memory cell transistors connected to a respective bit line, and gates of memory cell transistors of different memory cell transistor strings connected to a respective word line, the method comprising:

• (a) determining a tendency of a threshold voltage of a first memory cell transistor of the plurality of memory cell transistors to shift from a programmed state;
• (b) in response to the determining, selecting a first verification voltage from at least a set of verification voltages including the first verification voltage, a second verification voltage and a third verification voltage;
• and
• (c) programming the first memory cell transistor to alter the threshold voltage of the first memory cell transistor to a first range to store at least a bit of first data, the programming including verifying the threshold voltage of first memory cell transistor has been altered sufficiently using the first verification voltage, and programming a second memory cell to alter a threshold voltage of the second memory cell to the first range to store the at least a bit of the first data, including verifying the threshold voltage of the second memory cell has been altered sufficiently using one of the second verification voltage and third verification voltage.

A method of programming a row of memory cells, comprising:

• selecting a first row of memory cells among a plurality of rows;
• selecting a first subset of the memory cells of the first row to change a detectable characteristic of the first subset of the memory cells to within a first program state range, the first program state range representing a value of at least a first bit of data;
• programming the first subset of memory cells to change the characteristic of each of the first subset of the memory cells, including verifying the change of the characteristic of some of the first subset of memory cells with a first verification level, and verifying others of the first subset of memory cells with a second verification level that is different from the first verification level,
• wherein the first and second verification levels are selected in response to detecting a level of the detectable characteristic of each of the first subset of memory cells prior to programming the first subset of memory cells.

A method of programming a memory device, comprising:

• programming a first plurality of memory cells to a first program state of a plurality of program states, each program state representing a unique set of values of plural data bits, the first plurality of memory cells connected to a first word line, the programming comprising a plurality of program loops, each program loop comprising:
• (a) applying a program voltage to the word line;
• (b) applying a first verify voltage to the word line to verify a first subset of the first plurality of memory cells have at least a first threshold voltage;
• (c) applying a second verify voltage, different from the first verify voltage, to the word line to verify a second subset of the first plurality of memory cells have at least a second threshold voltage;
• and
• (d) applying a third verify voltage, different from the first and second verify voltages, to the word line to verify a third subset of the first plurality of memory cells have at least a third threshold voltage,
• wherein the first subset of memory cells, the second subset of memory cells and the third subset of memory cells have different tendencies of shifting of their respective threshold voltages
• wherein the first subset of memory cells is selected based upon a tendency of threshold voltages of the first subset to increase after programming,
• wherein the second subset of memory cells is selected based upon no significant tendency of the threshold voltages of the second subset to shift after programming,
• wherein the third subset of memory cells is selected based upon a tendency of threshold voltages of the third subset of memory cells to decrease after programming,
• and
• wherein the first verify voltage is less than the second verify voltage, and the second verify voltage is less than the third verify voltage.

A method of programming a multi-bit non-volatile memory cell comprising:

• programming a first bit of data into the memory cell so that the memory cell exhibits a characteristic within a first range, the exhibited characteristic representing the first bit of data;
• reading the first bit of data from the memory cell;
• determining a shift of the characteristic exhibited by the memory cell;
• and
• programming a the memory cell to store the first bit of data and a second bit of data so that the memory cell exhibits a characteristic within a second range, the second range being chosen based upon the determined shift.