Apparatus, System, and Method for Writing Multiple Magnetic Random Access Memory Cells with a Single Field Line

A memory device comprising:

• an array of magnetic random access memory (MRAM) cells including a plurality of rows and a plurality of columns;
• and
• a plurality of field lines;
• a field line controller configured to generate a plurality of write signals, each of the plurality of write signals traversing a corresponding one of the plurality of field lines;
• wherein:
• in a initial write cycle, each of the plurality of write signals writes concurrently to a corresponding one of the plurality of rows of MRAM cells such that each of at least a first subset of the plurality of columns of MRAM cells is configured to a first state;
• and
• in a subsequent write cycle, each of the plurality of write signals writes concurrently to the corresponding one of the plurality of rows of MRAM cells such that each of a second subset of the plurality of columns of MRAM cells is configured to an updated state, while each of the first subset of the plurality of columns of MRAM cells remains configured to the first state.

A memory device comprising:

• a plurality of magnetic random access memory (MRAM) cells;
• a field line;
• a field line controller configured to generate a write sequence on the field line, wherein the write sequence writes at least a subset of the plurality of MRAM cells to a first value during a first write cycle, and writes a remaining subset of the plurality of MRAM cells to a second value during a second write cycle;
• a plurality of bit lines;
• and
• a bit line controller, wherein:
• the bit line controller is configured to generate a first heating signal that traverses each of at least a subset of the plurality of bit lines electrically connected to corresponding ones of the at least a subset of the plurality of MRAM cells;
• the first heating signal heats each of the at least a subset of the plurality of MRAM cells for a heating time period during a first write cycle;
• the bit line controller is configured to generate a second heating signal that traverses each of a remaining subset of the plurality of bit lines electrically connected to corresponding ones of the remaining subset of the plurality of MRAM cells;
• and
• the second heating signal pre-heats each of the remaining subset of the plurality of MRAM cells for a pre-heating time period during the first write cycle, and heats the each of the remaining subset of the plurality of MRAM cells for a heating time period during the second write cycle that is shorter than the heating time period during the first write cycle, so that a duration of the second write cycle is shorter than a duration of the first write cycle.