Apparatuses and methods for determining stability of a memory cell
AssigneeMicron Technology, Inc.
InventorAlessandro Torsi
Life of this patent
Estimating the term…
Abstract
Examples described include apparatuses and methods for determining stability of memory cells. Resistance variable memory cells may be used. Once a memory cell is placed in a low or high resistance state responsive to set or reset pulses, the stability of the state may be determined, such as by providing another pulse to the memory cell or otherwise stressing the cell. The another pulse may be of an opposite polarity to the set or reset pulses already applied. If the memory cell is no longer in the target state after providing the another pulse, additional set or reset pulses may be applied to achieve a stable state.
Claims48
A method for determining stability a memory cell, the method comprising:
- providing a pulse to the memory cell to place the memory cell in a target state;
- determining a resistance of the memory cell after providing the pulse;
- if the resistance of the memory cell indicates the memory cell is in the target state, intentionally stressing the memory cell;
- determining a resistance of the memory cell after intentionally stressing the memory cell;
- and
- if the resistance of the memory cell indicates the memory cell is still in the target state, determining the memory cell is a stable memory cell.
A method for determining stability a memory cell, the method comprising:
- providing a first series of pulses to the memory cell to place the memory cell in a first state;
- if the memory cell is determined to be in the first state, providing another pulse to determine a stability of the memory cell in the first state;
- determining the resistance of the memory cell after providing the another pulse;
- if the resistance of the memory cell indicates the memory cell is still in the first state, providing a second series of pulses to the memory cell to place the memory cell in a second state.
A method comprising:
- determining whether a memory cell is in a target state;
- after determining that the memory cell is in the target state, determining whether the memory cell is in a stable state;
- and
- if the memory cell is determined to be in a stable state, determining the memory cell is a stable memory cell.
An apparatus comprising:
- a memory cell;
- and
- a controller configured to selectively cause the memory cell to be set and reset, wherein the controller is configured to cause a pulse to be provided to the memory cell to place the memory cell in a first state, wherein the controller is further configured to cause an additional pulse to be provided to the memory cell to determine whether the memory cell is stable in the first state, wherein the controller is further configured to cause a second pulse to be provided to the memory cell to place the memory cell in a second state, wherein the controller is further configured to cause a further pulse to be provided to the memory cell to determine whether the memory cell is stable in the second state.
An apparatus comprising:
- a resistance variable memory cell;
- and
- a controller configured to cause a pulse to be provided to the resistance variable memory to place the resistance variable memory cell in a target state, wherein the controller is further configured to cause the memory cell to be intentionally stressed to determine whether the memory cell is stable, wherein the controller is further configured to cause another pulse to be provided to the memory cell if the memory cell is determined to be not stable.
An apparatus comprising:
- a memory cell;
- and
- a controller configured to:
- determine whether the memory cell is in a target state;
- after determining that the memory cell is in the target state, determine whether the memory cell is in a stable state;
- and
- if the memory cell is determined to be in a stable state, determine the memory cell is a stable memory cell.
An apparatus comprising:
- a memory cell;
- and
- a controller configured to:
- cause a pulse to be provided to the memory cell to place the memory cell in a target state;
- determine a resistance of the memory cell after the pulse is provided;
- if the resistance of the memory cell indicates the memory cell is in the target state, cause the memory cell to be intentionally stressed;
- determine the resistance of the memory cell after the memory cell is intentionally stressed;
- and
- if the resistance of the memory cell indicates the memory cell is still in the target state, provide an indication the memory cell is a stable memory cell.
Dependencies are inferred from the claim text.