Method for driving semiconductor memory device

A method for driving a semiconductor memory device, the method comprising steps of:

• a step (a) of preparing the semiconductor memory device;
• wherein
• the semiconductor memory device comprises:
• at least two bit lines (BL);
• at least two word lines (WL);
• and
• at least four memory cells (5) disposed at intersections of each bit line (BL) and each word line (WL);
• wherein
• the at least two bit lines (BL) include a first bit line (BL1) and a second bit line (BL2);
• the at least two word lines (WL) include a first word line (WL1) and a second word line (WL2);
• the at least four memory cells (5) include first to fourth memory cells (51, 52, 53, 54);
• each memory cell (51, 52, 53, 54) comprises:
• a first gate electrode (12);
• a ferroelectric film (13);
• a semiconductor film (14);
• a source electrode (15s);
• a drain electrode (15d);
• a paraelectric film (16);
• and
• a second gate electrode (17);
• the ferroelectric film (13) is interposed between the first gate electrode (12) and the semiconductor film (14);
• the source electrode (15s) and the drain electrode (15d) are interposed between the semiconductor film (14) and the paraelectric film (16),
• the first gate electrode (12), the ferroelectric film (13), the source electrode (15s), and the drain electrode (15d) constitute a first semiconductor transistor (18);
• the second gate electrode (17), the paraelectric film (16), the source electrode (15s), and the drain electrode (15d) constitute a second semiconductor transistor (19);
• the first word line (WL1) comprises a first top gate word line (WTG1) and a first bottom gate word line (WGB1);
• the second word line (WL2) comprises a second top gate word line (WTG2) and a second bottom gate word line (WGB2);
• the first top gate word line (WTG1) is electrically connected to the second gate electrodes (17) of the first and second memory cells (51, 52);
• the first bottom gate word line (WBG1) is electrically connected to the first gate electrodes (12) of the first and second memory cells (51, 52);
• the second top gate word line (WTG2) is electrically connected to the second gate electrodes (17) of the third and fourth memory cells (53, 54);
• the second bottom gate word line (WBG2) is electrically connected to the first gate electrodes (12) of the third and fourth memory cells (53, 54);
• the first bit line (BL1) is electrically connected to the drain electrode (15d) of the first memory cell (51);
• the source electrode (15s) of the first memory cell (51) is electrically connected to the drain electrode (15d) of the third memory cell (53);
• the second bit line (BL2) is electrically connected to the drain electrode (15d) of the second memory cell (52);
• the source electrode (15s) of the second memory cell (52) is electrically connected to the drain electrode (15d) of the fourth memory cell (54);
• each of the first to third memory cells (51 to 53) has either a low resistance state or a high resistance state;
• and
• the fourth memory cell (54) has the high resistance state;
• a step (b) of applying voltages BL1V, BL2V, WBG1V, and WBG2V which satisfy the following relationship from time tB to time tC, while an ON voltage is applied to the first top gate word line (WTG1) and to the second top gate word line (WTG2), after the step (a), so as to maintain the states of the first to fourth memory cells (51 to 54);
• BL1V>BL2V
• WBG1V<BL1V
• WBG2V<BL1V
• WBG1V=BL2V, and
• WBG2V=BL2V
• where
• BL1V represents a voltage applied to the first bit line (BL1);
• BL2V represents a voltage applied to the second bit line (BL2);
• WTG1V represents a voltage applied to the first top gate word line (WTG1);
• WBG1V represents a voltage applied to the first bottom gate word line (WBG1);
• and
• WTG2V represents a voltage applied to the second top gate word line (WTG1);
• and
• WBG2V represents a voltage applied to the second bottom gate word line (WBG2);
• a step (c) of applying voltages BL1V, BL2V, WBG1V, and WBG2V which satisfy the following relationship from the time tC to time tD, while an ON voltage is applied to the first top gate word line (WTG1) and to the second top gate word line (WTG2), after the step (b), so as to maintain the states of the first to third memory cells (51 to 53), however, so as to vary the state of the fourth memory cell (54) from the high resistance state to the low resistance state;
• and
• BL1V>BL2V
• WBG1V<BL1V
• WBG2V=BL1V
• WBG1V=BL2V, and
• WBG2V>BL2V
• a step (d) of applying voltages BL1V, BL2V, WBG1V, and WBG2V which satisfy the following relationship from the time tD to time tE, while an ON voltage is applied to the first top gate word line (WTG1) and to the second top gate word line (WTG2), after the step (c), so as to maintain the states of the first to fourth memory cells (51 to 54);
• BL1V>BL2V
• WBG1V<BL1V
• WBG2V<BL1V
• WBG1V=BL2V, and
• WBG2V=BL2V
• wherein
• an inequality set:
• t1<tD−tC<tE−tB<t2 is satisfied;
• where
• t1 represents time necessary for the memory cell to vary from the high resistance state to the low resistance state;
• and
• t2 represents time necessary for the memory cell to vary from the low resistance state to the high resistance state.