3d memory and decoding technologies

A memory device, comprising:

• a plurality of bit lines in a first plane;
• a plurality of select lines in a second plane parallel with the first plane;
• an array of pillar select devices, the access devices in the array being disposed at corresponding cross-points of the plurality of bit lines and select lines, each having a first terminal connected to a bit line at the corresponding cross-point, a second terminal connected to a select line at the corresponding cross-point, and a third terminal;
• an array of conductive pillars, conductive pillars in the array being connected to the third terminal of a corresponding access device in the array of access devices;
• a 3D array of sidewall memory elements comprising transition metal oxide characterized by built in self-switching, the sidewall memory elements in the 3D array disposed on sides of the conductive pillars in the array, including a plurality of sidewall memory elements on each pillar, the sidewall memory elements in the 3D array comprising programmable and erasable memory material;
• a plurality of pairs of word line structures orthogonal to the array of conductive pillars, each pair being disposed at a corresponding level of the 3D array, and a given pair of word line structures in a level including:
• a first word line structure including a first set of word lines coupled together at a first word line pad for the level, each word line in the first set being connected to side wall memory elements between alternating rows of conductive pillars in said array of conductive pillars;
• and
• a second word line structure including a second set of word lines coupled together at a second word line pad for the level, and interleaved with the word lines in the first set of word lines, each word line in the first set being connected to side wall memory elements between alternating rows of conductive pillars in said array of conductive pillars.

A method for manufacturing a memory device, comprising:

• forming an array of access devices;
• forming a plurality of patterned conductor layers, separated from each other and from the array of access devices by insulating layers, the plurality of patterned conductor layers including left side and right side conductors;
• forming an array of conductive pillars extending through the plurality of patterned conductor layers, the conductive pillars in the array contacting corresponding access devices in the array of access devices, and defining left side and right side interface regions between the conductive pillars and the left side and right side conductors in corresponding patterned conductor layers in the plurality of patterned conductor layers;
• and
• forming memory elements in the left side and right side interface regions, each of said memory elements comprising a transition metal oxide, by oxidizing the left side and right side conductors in each layer.