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AssigneeMosaid Technologies Incorporated
InventorRoland Schuetz
Estimating the term…
A system comprising a plurality of memory devices coupled by a common bus to a controller has a single serially coupled enable signal per channel. Each memory device or chip comprises a serial enable input and enable output and a register for storing a device identifier, e.g., chip ID. The memory devices are serially coupled by a serial enable link, for assertion of a single enable signal to all devices. This parallel data and serial enable configuration provides reduced per-channel pin count, relative to conventional systems that require a unique enable signal for each device. In operation, commands on the common bus targeting an individual device are asserted by adding an address field comprising a device identifier to each command string, preferably in an initial identification cycle of the command. Methods are also disclosed for initializing the system, comprising assigning device identifiers and obtaining a device count, prior to normal operation.
A system comprising a controller and a plurality of (N) memory devices, N being an integer greater than one, the plurality of memory devices being
A system comprising a plurality of memory devices and a controller, wherein:
A memory device comprising:
A method of operating a system comprising a plurality of (N) memory devices and a controller, the plurality of memory devices being interconnected to the controller by a common bus comprising parallel links, each memory device comprising a serial enable input and serial enable output, each of the plurality of the memory devices being coupled serially through a single serial enable link from an enable output of the controller, the method comprising:
A method of addressing individual memory devices for controlling data transfer in a system comprising a controller and a plurality of memory devices that are interconnected by a parallel link and wherein the plurality of memory devices are connected in series by a serial enable link from the controller, the method comprising:
A memory system comprising:
A memory controller for controlling a channel of a memory system comprising a plurality of memory devices, the controller comprising:
Dependencies are inferred from the claim text.
From the US filing history. Foreign family members aren’t listed.
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Details of stores covered by group G11C11/00: arrangements for interconnecting storage elements electrically, e.g. by wiring
On a parallel bus: being a memory bus
Bus transfer protocol, e.g. handshake; Synchronisation: on a daisy chain bus
Arrangements for writing information into, or reading information out from, a digital store: input/output [I/O] data interface arrangements, e.g.…
Term end not estimated
The present invention relates to semiconductor devices, and more particularly to systems, apparatus and methods for connection of a plurality of memory devices with a function of chip enable or device selection.
Memory systems comprising one or more memory devices are widely used in digital equipment including consumer devices, such as computers, portable audio/video systems, cameras, solid state drives (SSDs) and the like. Memory devices include non-volatile memories, such as, for example, flash memories and volatile memories, such as, for example, dynamic random access memories (DRAMs). For example, non-volatile memories such as flash memories or high speed volatile DRAMs are used for the memory devices, depending on the application or task required. Flash memories are implemented, for example, as NOR flash or NAND flash memories. NAND flash memory provides for a higher memory density per area due to its more compact memory array structure.
SSDs comprising flash memory devices, such as, for example, NAND flash memories, provide high density memories that are non-volatile and compact relative to conventional hard disk drives. Large capacity memory systems may be provided by interconnecting multiple flash memory devices, typically using a common bus, i.e., a parallel data bus architecture. Such systems comprise a memory controller and a parallel multidrop bus with 8, 10 or more flash memory devices per bus, for example. Systems comprising a memory controller and serially interconnected memory devices arranged in a ring or loop for serial data transfer are also known. The memory controller provides logic for interfacing a memory device to a host system, comprising a processor, for data storage and retrieval.
Embodiments of the present invention will now be described, by way of example only, with reference to the following drawings:
FIG. 1A shows a block diagram illustrating a system comprising a host system including a processor, a memory controller and a memory system comprising a plurality of memory devices, to which embodiments of the present invention are applicable;
FIG. 1B shows a block diagram of a memory system including a plurality of memory devices and a controller connected to the plurality of memory devices via a common bus to which embodiments of the present invention are applicable;
To form a large capacity memory system, as illustrated schematically in FIGS. 1A and 1B, multiple semiconductor memory devices, such as, for example, flash memory devices, are typically interconnected in parallel. Alternatively, memory devices can be serially interconnected as illustrated schematically in FIG. 1C. In such systems, the memory devices can be any type of flash memories, e.g., NAND, NOR, or AND type flash memories. Also, the memory devices can be random access memories, e.g., SRAMs, DRAMs, or other known types of memory devices, of the same or mixed type.
Systems according to embodiments of the present invention are directed to parallel bus memory systems. As a starting point, relevant details of a conventional parallel bus system will be described with reference to FIG. 2. By way of example only, a system according to an embodiment of the present invention comprising a plurality of flash memory devices will be described with reference to the FIGS. 3 to 13. This system provides for an enable signal as a single device or chip enable signal, CEb, for addressing a plurality of such memory devices, with reduced per-channel pin count.
Referring first to FIG. 1A, this figure illustrates an exemplary system 100 comprising a host system 102, comprising a processor 103, connected to a memory system 106 via a controller 104 for controlling the memory system. The memory system 106 comprises a plurality of memory devices, e.g., two flash memory devices 107-0 and 107-1, s as shown. The controller 104 receives requests from the host system 102 and translates the requests into commands that are interpretable by the memory system 106. The controller 104 also translates logical addresses into physical addresses of memory system 106 that are used by the host system 102 for storage and retrieval of data in memory banks of memory devices 107-0, 107-1.