Latch circuit and display device

A latch circuit for holding and latching data when a scanning voltage is input, the circuit comprising:

• an input transistor having first and second electrodes and a gate, the first electrode being applied with a voltage corresponding to “0” or “1”, the input transistor outputting the voltage from the second electrode when the scanning voltage is input to the gate;
• a retention capacitance retaining a voltage output by the input transistor, and having a first electrode and a second electrode, the second electrode being applied with a fixed voltage and the first electrode being connected to a second electrode of the input transistor;
• a first transistor which is one of n type and p type transistors having a gate connected to the second electrode of the input transistor, a first electrode applied with a first latch control signal and a second electrode connected to a first output terminal;
• a second transistor which is the other of n type and p type transistors having a gate connected to the second electrode of the first transistor, a first electrode input with a second latch control signal and a second electrode connected to a second output terminal;
• and
• a diode connected between a first electrode and a second electrode of the first transistor and becomes a conducting state corresponding to a change in a voltage level of the first latch control signal;
• wherein
• voltage levels of the first latch control signal and the second latch control signal are respectively changed at a certain timing, so that a voltage of the first output terminal and a voltage of the second output terminal are changed to a voltage corresponding to “0” or “1” and latched

A latch circuit for holding and latching data when a scanning voltage is input, the circuit comprising:

• an input transistor having first and second electrodes and a gate, the first electrode being applied with a voltage corresponding to “0” or “1”, the input transistor outputting the voltage from the second electrode when the scanning voltage is input to the gate;
• a retention capacitance retaining a voltage output by the input transistor, and having a first electrode and a second electrode, the second electrode being applied with a fixed voltage and the first electrode being connected to a second electrode of the input transistor;
• a first transistor which is one of n type and p type transistors having a gate connected to the second electrode of the input transistor, a first electrode and a second electrode connected to a first output terminal;
• a second transistor which is the other of n type and p type transistors having a gate connected to the second electrode of the first transistor, a first electrode input with a second latch control signal and a second electrode connected to a second output terminal;
• a fourth transistor as same type as the first transistor having a gate input with a third latch control signal, a first electrode input with the first latch control signal and a second electrode connected to the first electrode of the first transistor;
• and
• a diode connected between the second electrode of the first transistor and the first electrode of the fourth transistor, the diode becoming a conducting state corresponding to a change in a voltage level of the first latch control signal;
• wherein
• voltage levels of the first latch control signal, the second latch control signal and the third latch control signal are respectively changed at a certain timing, so that a voltage of the first output terminal and a voltage of the second output terminal are changed to a voltage corresponding to “0” or “1” and latched.