Reduced voltage swing clock distribution

A method comprising:

• providing a first plurality of non-overlapping clock signals;
• transitioning a clock signal of at least one of a second plurality of clock signals from a first voltage level to an intermediate voltage level that is between a power supply voltage and a ground reference, in response to detecting a rising edge of a first one of the first plurality of clock signals;
• preventing said clock level from reaching one of the power supply voltage or the ground reference by holding said clock signal at the intermediate voltage level for at least a pulse width of a second one of the first plurality of clock signals;
• and
• transitioning said clock signal back to the first voltage level in response to a rising edge of a third one of the first plurality of clock signals.

An apparatus comprising:

• circuitry;
• and
• a clock distribution network configured to provide at least one input clock to the circuitry;
• wherein the circuitry includes:
• an interface to the clock distribution network configured to receive an input clock from the clock distribution network;
• a clock generator configured to provide a first plurality of clock signals based upon the received input clock;
• and
• a reduced voltage swing clock generator, wherein the reduced voltage swing clock generator is configured to:
• transition a clock signal of at least one of a second plurality of clock signals from a first voltage level to an intermediate voltage level that is between a power supply voltage and a ground reference, in response to detecting a rising edge of a first one of the first plurality of clock signals;
• prevent said clock signal from reaching one of the power supply voltage or the ground reference by holding said clock signal at the intermediate voltage level for at least a pulse width of a second one of the first plurality of clock signals;
• and
• transition said clock signal back to the first voltage level in response to detecting a rising edge of a third one of the first plurality of clock signals.

An integrated circuit comprising:

• one or more sequential elements;
• and
• a clock tree configured to provide one or more clock signals to each one of the one or more sequential elements;
• wherein the clock tree includes:
• a clock generator configured to provide a first plurality of clock signals;
• a reduced voltage swing clock generator configured to receive the first plurality of clock signals, wherein the reduced voltage swing clock generator is configured to:
• transition a clock signal of at least one of a second plurality of clock signals from a first voltage level to an intermediate voltage level that is between a power supply voltage and a ground reference, in response to detecting a rising edge of a first one of the first plurality of clock signals;
• prevent said clock signal from reaching one of the power supply voltage or the ground reference by holding said clock signal at the intermediate voltage level for at least a pulse width of a second one of the first plurality of clock signals;
• and
• transition said clock signal back to the first voltage level in response to detecting a rising edge of a third one of the first plurality of clock signals.