Binary half-adder using oscillators
AssigneeManchester Metropolitan University
InventorsStephen Lynch, Jon Borresen
Life of this patent
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Abstract
A binary half-adder comprising first and second oscillators, each oscillator being connected to a first input and to a second input, the second oscillator being connected to the first oscillator, wherein the first oscillator is configured to oscillate if the first input is high or the second input is high, the second oscillator is configured to oscillate if the first and the second inputs are high, and wherein the connection between the second oscillator and the first oscillator is configured to suppress oscillation of the first oscillator if the second oscillator is oscillating.
Claims18
A binary half-adder comprising first and second oscillators, each oscillator being connected to a first input and to a second input, the second oscillator being connected to the first oscillator, wherein the first oscillator is configured to oscillate if the first input is high or the second input is high, the second oscillator is configured to oscillate if the first and the second inputs are high, and wherein the connection between the second oscillator and the first oscillator is configured to suppress oscillation of the first oscillator 1f the second oscillator is oscillating.
A binary adder comprising:
- a first binary half-adder;
- a second binary half-adder;
- the binary half-adders being combined together with an additional oscillator.
A binary adder comprising:
- a binary half-adder comprising first and second oscillators;
- a third oscillator which is connected to the second oscillator, the connection between the third oscillator and the second oscillator being configured to suppress oscillation of the second oscillator if the third oscillator is oscillating;
- wherein the first, second and third oscillators are each connected to first, second and third inputs, the first oscillator being configured to oscillate if any of the first, second or third inputs are high, the second oscillator being configured to oscillate if any two of the first, second or third inputs are high, and the third oscillator being configured to oscillate if the first, second and third inputs are high.
A binary half-adder comprising first and second oscillators, each oscillator being connected to a first input and to a second input, the second oscillator being connected to an output of the first oscillator, wherein the first oscillator is configured to oscillate if the first input is high or the second input is high, the second oscillator is configured to oscillate if the first and the second inputs are high, and wherein the first and second oscillators are configured to oscillate at the same frequency, and the connection between the second oscillator and the output of the first oscillator is configured that the output from the second oscillator will combine in anti-phase with the output from the first oscillator when the first and second oscillators are oscillating.
An apparatus comprising a first oscillator connected to a second oscillator, the connection between the second oscillator and the first oscillator being configured to suppress oscillation of the first oscillator if the second oscillator is oscillating, wherein the first oscillator is connected to a power supply such that the first oscillator will oscillate unless oscillation of the first oscillator is suppressed by the second oscillator.
Dependencies are inferred from the claim text.