Integrated Circuit Having Receiver Jitter Tolerance ("JTOL") Measurement
AssigneeRambus Inc.
InventorsHae-Chang Lee, Jaeha Kim, Brian Leibowitz
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Abstract
An integrated circuit capable of on-chip jitter tolerance measurement includes a jitter generator circuit to produce a controlled amount of jitter that is injected into at least one clock signal, and a receive circuit to sample an input signal according to the at least one clock signal. The sampled data values output from the receiver are used to evaluate the integrated circuit's jitter tolerance.
Claims29
An integrated circuit, comprising:
- a jitter generator circuit to produce a jitter signal having controlled characteristics that is injected into at least one clock signal;
- and
- a receive circuit to sample an input signal according to the at least one clock signal having the jitter signal, the receive circuit outputting sampled data values that are used to obtain a bit-error-ratio.
An integrated circuit, comprising:
- circuitry to sample an input signal according to a sampling clock, to generate data samples;
- a clock source to generate the sampling clock;
- circuitry to compare expected data values with the data samples and to generate an error indication in dependence on whether the expected data values match the data samples;
- and
- circuitry to inject jitter into the sampling clock to simulate jitter in the input signal.
The integrated circuit of 9, where the circuitry to inject jitter is operable to inject at least one of sinusoidal jitter (Si) or random jitter (RJ).
The integrated circuit of claim 26, where the pattern generator is a self-seeded PRBS generator.
An integrated circuit comprising:
- a receiver to sample an input signal to the integrated circuit to generate data samples;
- and
- a clock recovery circuit to generate a recovered clock;
- wherein
- the receiver is to sample the input signal in dependence on the recovered clock,
- the integrated circuit is to operate in a first mode in which the clock recovery circuit generates the recovered clock in dependence on transitions in the input signal and a control signal, the control signal representing noise to be injected into the recovered clock, such that the recovered clock experiences time-varying offset relative to transitions in the input signal, and
- the integrated circuit is also to operate in a second mode in which the clock recovery circuit generates the recovered clock in dependence on the transitions in the input signal but not in dependence on the control signal, the integrated circuit further comprising circuitry to in the second mode compare expected data values with the data samples and to generate an error indication in dependence on whether the expected data values match the data samples.
A method of testing jitter tolerance of an integrated circuit in receiving a data-conveying input signal, comprising:
- using a data clock in a first mode to sample the input signal;
- and
- in a second mode,
- injecting a controlled amount of jitter into the data clock to generate a noisy data clock,
- using the noisy data clock to sample the input signal to generate samples, and
- comparing the samples with expected data to detect errors in the samples.
Dependencies are inferred from the claim text.