Semiconductor device with damascene bit line and method for fabricating the same
AssigneeSK hynix Inc.
InventorNam-Yeal LEE
Life of this patent
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Abstract
A semiconductor device includes a substrate having a plurality of contact surfaces, an interlayer dielectric layer formed over the substrate and having a first open portion which exposes a part of the contact surfaces and a second open portion which exposes the other contact surfaces, a storage node contact (SNC) plug filling the first open portion, and a damascene structure filing the second open portion and including a bit line, a spacer formed on both sidewalls of the bit line, a capping layer formed over the bit line and the spacer, and an air gap formed between the bit line and the spacer. The bit line includes a conductive material of which the volume is contracted by a heat treatment to form the air gap.
Claims20
A semiconductor device comprising:
- a substrate having a plurality of contact surfaces;
- an interlayer dielectric layer formed over the substrate and having a first open portion which exposes a part of the contact surfaces and a second open portion which exposes the other contact surfaces;
- a storage node contact (SNC) plug filling the first open portion;
- and
- a damascene structure filing the second open portion and comprising a bit line, a spacer formed on both sidewalls of the bit line, a capping layer formed over the bit line and the spacer, and an air gap formed between the bit line and the spacer.
A method for fabricating a semiconductor device, comprising:
- forming an interlayer dielectric layer over a semiconductor substrate;
- forming an open portion by etching the interlayer dielectric layer;
- forming a damascene structure including a bit line partially filling the open portion, a spacer formed on both sidewalls of the bit line, and a capping layer formed over the bit line;
- and
- contracting the bit line through annealing to form an air gap between the bit line and the spacer.
A method for fabricating a semiconductor device, comprising:
- forming a preliminary first conductive pattern over a semiconductor substrate;
- forming an open portion to separate the preliminary first conductive pattern into independent first conductive patterns;
- forming a damascene structure in the open portion, wherein the damascene structure includes a second conductive pattern partially filling the open portion, a spacer formed on both sidewalls of the second conductive pattern, and a capping layer formed over the second conductive pattern;
- and
- contracting the second conductive pattern through annealing to form an air gap between the second conductive pattern and the spacer.
A method for fabricating a semiconductor device, comprising:
- forming an interlayer dielectric layer over a semiconductor substrate;
- forming a first open portion by etching the interlayer dielectric layer;
- forming a preliminary storage node contact (SNC) plug within the first open portion;
- forming a second open portion to separate the preliminary SNC plug into independent SNC plugs;
- forming a damascene structure in the second open portion, wherein the damascene includes a bit line partially filling the second open portion, a spacer formed on both sidewalls of the bit line, and a capping layer formed over the bit line;
- and
- contracting the bit line through annealing to form an air gap between the bit line and the spacer.
Dependencies are inferred from the claim text.