Three-Dimensional Vertical Interconnecting Structure and Manufacturing Method Thereof

A fabricating method for a three-dimensional vertically interconnected structure, characterized by comprising steps of:

• S1, conducting lithography on the surface of a single layer of silicon wafer or chip which has or has not undergone a thinning process to form photo-resist mask for annular patterns, then sequentially etching a dielectric layer and a substrate layer of the single layer of wafer or chip to form a first concave of fergitun-shape;
• S2, depositing a barrier layer and a seed layer to cover an inside wall of the first concave, and then copper electroplating to fill the first concave, for forming a first electrical conductive ring;
• S3, forming a redistribution layer which connects the first electrical conductive ring with microelectronic devices inside the wafer or chip, wherein the redistribution layer comprises a dielectric layer and a metallic interconnection layer;
• S4, etching the dielectric layer of the redistribution layer and the dielectric layer of the wafer or chip sequentially to form a first through-silicon-via (TSV) inside the first electrical conductive ring, wherein the first TSV has the same radius and center as the inner ring of the first electrical conductive ring;
• S5, sequentially stacking single layers of wafers or chips which have completed steps S1-S4 and aligning the same, and adjacent wafers or chips being adhered to each other by using organics or metallic solders;
• S6, depositing a seed layer and electroplating copper on one side of the multi-stacked layers of wafers or chips to seal a first through layers of wafers or chips hole that is constituted of vertically aligned TSVs;
• filling the first through layers of wafers or chips holes which penetrate the multi-layered stacks from bottom to top with copper electroplating to form a first micro electrical conductive pole, and removing the electroplated copper and seed layer, for finishing the fabrication of the three-dimensional vertically interconnected structure.

A fabricating method for a three-dimensional vertically interconnected structure, characterized by comprising steps of:

• S1, conducting lithography on a front surface of a single layer of silicon wafer or chip to form a photo-resist mask for annular patterns, then sequentially etching a dielectric layer and a substrate layer of the single layer of wafer or chip to form a first concave of fergitun-shape;
• S2, depositing a barrier layer and a seed layer to cover the inside wall of the first concave, and electroplating copper to fill the first concave, for forming a first electrical conductive ring;
• S3, forming a redistribution layer which connects the first electrical conductive ring with microelectronic devices inside the wafer or chip, wherein the redistribution layer comprises a dielectric layer and a metallic interconnection layer;
• S4, sequentially etching the dielectric layer of the redistribution layer and the dielectric layer of the wafer or chip to form a blind TSV inside the first electrical conductive ring, the blind TSV having the same radius and center as the inner ring of the first conductive ring;
• S5, stacking two layers of wafers or chips which have completed steps S1-S4 face-to-face and aligning the same, wherein the wafers or chips being adhered to each other by using organics or metallic solders;
• S6, conducting a thinning process on both sides of the layers of wafers or chips which are stacked until the blind TSVs of each layer of wafer or chip is exposed to implement a through layers of wafers or chips hole;
• S7, stacking a single layer of wafer or chip which has completed steps S1-S4 on the wafers or chips which have completed steps S1-S6, and adhering the same, and then repeating step S6 to implement a stacking of three or more layers of wafers or chips;
• S8, depositing a seed layer and conducting copper electroplating on one side of the stacked wafers or chips to seal the through layers of wafers or chips hole;
• filling the through layers of wafers or chips holes which penetrate the stacked wafers or chips from bottom to top with copper electroplating to form a micro electrical conductive pole, and removing the electroplated copper and the seed layer, for finishing the fabrication of the three-dimensional vertically interconnected structure.