Multi-chip package and method of manufacturing the same

A method of manufacturing a multi-chip package, the method comprising:

• providing a package substrate including a plurality of substrate pads disposed on an upper surface of the package substrate, the substrate pads including at least a ground pad and at least a signal pad;
• stacking a first semiconductor chip on the package substrate, the first semiconductor chip including at least a first bonding pad disposed on an upper surface of the first semiconductor chip;
• stacking at least a second semiconductor chip on the first semiconductor chip such that the first bonding pad remains exposed, the second semiconductor chip including at least a second bonding pad disposed on an upper surface of the second semiconductor chip;
• forming a first stud bump on an upper surface of the first bonding pad;
• forming a first conductive wire to extend from the substrate pad to an upper surface of the first stud bump;
• forming a first nail head bonding bump on the first stud bump and first conductive wire;
• and
• after the first semiconductor chip has been electrically connected to a ground:
• forming a second stud bump on an upper surface of the second bonding pad;
• and
• forming a second conductive wire extending from an upper surface of the first nail head bonding bump to the second stud bump.

A method of manufacturing a multi-chip package, comprising:

• providing a package substrate including a plurality of substrate pads disposed on an upper surface of the package substrate, the substrate pads including at least a ground pad and at least a signal pad;
• stacking a first semiconductor chip on the package substrate, the first semiconductor chip including at least a first bonding pad disposed on an upper surface of the first semiconductor chip;
• stacking at least a second semiconductor chip on the first semiconductor chip such that the first bonding pad remains exposed, the second semiconductor chip including at least a second bonding pad disposed on an upper surface of the second semiconductor chip;
• forming a first electrical connection between the first semiconductor chip and a ground pad on the package substrate, an end of the electrical connection being formed on a first conductive bump of the first semiconductor chip;
• and
• after electrically connecting the first semiconductor chip to a ground pad, forming a second electrical connection from the first semiconductor chip to the second semiconductor chip,
• wherein the step of forming a second electrical connection from the first semiconductor chip to the second semiconductor chip comprises the steps of:
• forming a second conductive bump on the end of the first electrical connection disposed on the first conductive bump of the first semiconductor chip;
• forming a first conductive bump on the second semiconductor chip;
• and
• forming a first conductive wire extending from the second conductive bump of the first semiconductor chip to the first conductive bump on the second semiconductor chip.