Low impedance gate control method and apparatus
AssigneeInfineon Technologies AG
InventorsReinhold Bayerer, Daniel Domes
Life of this patent
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Abstract
According to one embodiment of a module, the module includes a plurality of gate driver chips coupled in parallel and having a common gate input, a common supply voltage and a common output. The chips are spaced apart from one another and have a combined width extending between an edge of a first outer one of the chips and an opposing edge of a second outer one of the chips. The module further includes a plurality of capacitors coupled in parallel between ground and the common supply voltage, and a transverse electromagnetic (TEM) transmission line medium coupled to the common output of the chips and having a current flow direction perpendicular to the combined width of the chips.
Claims21
A module, comprising:
- a plurality of gate driver chips coupled in parallel and having a common gate input, a common supply voltage and a common output, the plurality of chips being spaced apart from one another and having a combined width extending between an edge of a first outer one of the chips and an opposing edge of a second outer one of the chips;
- a plurality of capacitors coupled in parallel between ground and the common supply voltage;
- and
- a transverse electromagnetic (TEM) transmission line medium coupled to the common output of the plurality of chips and having a current flow direction perpendicular to the combined width of the plurality of chips.
A module, comprising:
- a plurality of power transistor chips coupled in parallel and having a common gate input, a common supply voltage and a common output, the plurality of chips being spaced apart from one another and having a combined width extending between an edge of a first outer one of the chips and an opposing edge of a second outer one of the chips;
- a plurality of capacitors coupled in parallel between ground and the common supply voltage;
- and
- a transverse electromagnetic (TEM) transmission line medium coupled to the common gate input of the plurality of chips and having a current flow direction perpendicular to the combined width of the plurality of chips.
A power transistor system, comprising:
- a plurality of gate driver chips coupled in parallel and having a common gate input, a common supply voltage and a common output;
- a first plurality of capacitors coupled in parallel between ground and the common supply voltage of the plurality of gate driver chips;
- a plurality of power transistor chips coupled in parallel and having a common gate input, a common supply voltage and a common output, the plurality of power transistor chips being spaced apart from one another and having a combined width extending between an edge of a first outer one of the power transistor chips and an opposing edge of a second outer one of the power transistor chips;
- a second plurality of capacitors coupled in parallel between ground and the common supply voltage of the plurality of power transistor chips;
- and
- at least one transverse electromagnetic (TEM) transmission line medium coupling the common gate input of the plurality of power transistor chips to the common output of the plurality of gate driver chips, and having a current flow direction perpendicular to the combined width of the plurality of power transistor chips.
Dependencies are inferred from the claim text.