Semiconductor device
AssigneeRenesas Electronics Corporation
InventorsHiroaki OHKUBO, Yasutaka NAKASHIBA
Life of this patent
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Abstract
A semiconductor device includes a signal output unit, and a decision unit. The signal output unit includes m (≧2) pieces of fuses, a NAND gate, resistance elements, and an output terminal. The decision unit decides whether n or more pieces (m≧n≧2) of fuses are disconnected out of the m pieces of fuses included in the signal output unit, and outputs the result of a decision. When m=n=2, the decision unit is constituted of a NOR gate having two input terminals connected to a respective end of the fuses. Thus, a H-level potential signal is output at an output terminal of the NOR gate when the decision result is affirmative. On the other hand, when the decision result is negative, a L-level potential signal is output at the output terminal.
Claims12
A semiconductor device, comprising:
- a first unit including a first input terminal and a second input terminal;
- a second unit including a third input terminal and a fourth input terminal;
- a first wire connected to the first input terminal and the third input terminal;
- a second wire connected to the second input terminal and the fourth input terminal;
- a first resistor connected at a first end to the first wire;
- a second resistor connected at a first end to the second wire;
- a first fuse connected to the first wire;
- and
- a second fuse connected to the second wire, wherein
- both the first fuse and the second fuse are blown,
- the first unit outputs a first signal if both the first fuse and the second fuse are blown,
- the first unit outputs a second signal if neither the first fuse nor the second fuse is blown or if one of the first fuse and the second fuse is not blown,
- the second signal is at a different level from the first signal,
- the second unit outputs a third signal if both the first fuse and the second fuse are blown or if one of the first fuse and the second fuse is blown,
- the second unit outputs a fourth signal if neither the first fuse nor the second fuse is blown, and
- the fourth signal Is at a different level from the third signal.
A semiconductor device, comprising:
- a first unit including a first input terminal and a second input terminal;
- a second unit including a third input terminal and a fourth input terminal;
- a first wire connected to the first input terminal and the third input terminal;
- a second wire connected to the second input terminal and the fourth input terminal;
- a first resistor connected at a first end to the first wire;
- a second resistor connected at a first end to the second wire;
- a first antifuse connected to the first wire;
- and
- a second antifuse connected to the second wire, wherein
- both the first antifuse and the second antifuse are blown,
- the first unit outputs a first signal if both the first antifuse and the second antifuse are blown,
- the first unit outputs a second signal if neither the first antifuse nor the second antifuse is blown or if one of the first antifuse and the second antifuse is not blown,
- the second signal is at a different level from the first signal,
- the second unit outputs a third signal if both the first antifuse and the second antifuse are blown or if one of the first antifuse and the second antifuse is blown,
- the second unit outputs a fourth signal if neither the first antifuse nor the second antifuse is blown, and
- the fourth signal is at a different level from the third signal.
A semiconductor device, comprising:
- a NOR gate including a first input terminal and a second input terminal;
- a NAND gate including a third input terminal and a fourth input terminal;
- a first wire connected to the first input terminal and the third input terminal;
- a second wire connected to the second input terminal and the fourth input terminal;
- a first resistor connected at a first end to the first wire;
- a second resistor connected at a first end to the second wire;
- a first fuse connected to the first wire;
- and
- a second fuse connected to the second wire, wherein
- both the first fuse and the second fuse are blown.
A semiconductor device, comprising:
- a NOR gate including a first input terminal and a second input terminal;
- a NAND gale including a third input terminal and a fourth input terminal;
- a first wire connected to the first input terminal and the third input terminal;
- a second wire connected to the second input terminal and the fourth input terminal:
- a first resistor connected at a first end to the first wire;
- a second resistor connected at a first end to the second wire;
- a first antifuse connected to the first wire;
- and
- a second antifuse connected to the second wire, wherein
- both the first antifuse and the second antifuse are blown.
Dependencies are inferred from the claim text.